公开(公告)号：US09318466B2

公开(公告)日：2016-04-19

申请号：US14471620

申请日：2014-08-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Saket Chadda ,  Ramakanth Alapati ,  Adam Beece

IPC: H01L25/00 ,  H01L25/065

CPC classification number: H05K1/18 ,  H01L23/14 ,  H01L23/142 ,  H01L23/147 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/16 ,  H01L25/50 ,  H01L27/016 ,  H01L2224/131 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06589 ,  H05K1/032 ,  H05K1/053 ,  H05K1/115 ,  H05K1/16 ,  H05K1/181 ,  H05K3/4053 ,  H05K3/445 ,  H05K3/4644 ,  H05K2201/032 ,  H01L2924/014

Abstract: A methodology for a thin, flexible substrate having integrated passive circuit elements, and the resulting device are disclosed. Embodiments may include integrating one or more passive circuit components on a first or second surface of a substrate, and interconnecting one or more integrated circuit (IC) dies on a second surface of the interposer to the one or more passive circuit components with one or more metal-filled vias between the first and second surfaces, the first and second surfaces being opposite surfaces of the substrate.

Abstract translation: 公开了一种用于具有集成无源电路元件的薄柔性基板的方法，以及所得到的器件。 实施例可以包括在衬底的第一或第二表面上集成一个或多个无源电路部件，以及将一个或多个无源电路部件与一个或多个内插器的第二表面上的一个或多个集成电路（IC）管芯互连 在第一和第二表面之间的金属填充的通孔，第一和第二表面是基板的相对表面。

公开(公告)号：US09123787B2

公开(公告)日：2015-09-01

申请号：US14028729

申请日：2013-09-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Himani S. Kamineni ,  Ramakanth Alapati ,  Maria Balicka

IPC: H01L21/768 ,  H01L23/498 ,  G06F17/50

CPC classification number: H01L21/76897 ,  G06F17/5077 ,  H01L23/481 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Exemplary embodiments of the present invention provide a V0 via unit cell with multiple keep out zones. The keep out zones are oriented concentrically and provide support for multiple sizes of through-silicon vias (TSVs). An off-center alignment between the V0 via unit cell and a probe pad is used to improve contact between the V0 vias and a probe pad. During a chip redesign, the TSV size may be changed without the need to revise the V0 mask.

Abstract translation: 本发明的示例性实施例提供具有多个保持区的V0通孔单元。 保留区域同心取向，并提供对多种尺寸的通硅通孔（TSV）的支持。 使用V0通孔单元和探针焊盘之间的偏心对准来改善V0通孔和探针焊盘之间的接触。 在重新设计芯片期间，可以改变TSV大小，而无需修改V0掩码。

公开(公告)号：US09553080B1

公开(公告)日：2017-01-24

申请号：US14858373

申请日：2015-09-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Luke England ,  Ramakanth Alapati

IPC: H01L21/00 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L25/50 ,  H01L21/76898 ,  H01L23/522 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/15311 ,  H01L2924/16152

Abstract: Methods for integrating MOL TSVs in 3D SoC devices including face-to-face bonded IC chips. Embodiments include providing a device layer in each of IC chips on upper surfaces of top and bottom silicon wafers; forming, subsequent to the device layer, through-silicon vias (TSVs) extending through an upper surface of the device layer in each of the IC chips and into the bottom Si wafer; forming, subsequent to the TSVs, a dielectric layer on the upper surface of the device layer in each of the IC chips of the top and bottom Si wafers; forming a back-end-of-line metal layer in the dielectric layer of each of the IC chips of the top and bottom Si wafers; face-to-face bonding of opposing IC chips of the top and bottom Si wafers; and dicing adjacent bonded IC chips through vertically aligned dicing lanes in the top and bottom Si wafers.

Abstract translation: 将MOL TSVs集成到3D SoC设备中的方法，包括面对面粘合的IC芯片。 实施例包括在顶部和底部硅晶片的上表面上的每个IC芯片中提供器件层; 在器件层之后形成穿过每个IC芯片中的器件层的上表面并进入底部Si晶片的穿硅通孔（TSV）; 在TSV之后形成在顶部和底部Si晶片的每个IC芯片中的器件层的上表面上的介电层; 在顶部和底部Si晶片的每个IC芯片的电介质层中形成后端金属层; 顶部和底部Si晶片的相对IC芯片的面对面接合; 并通过顶部和底部Si晶片中的垂直排列的切割通道切割相邻的粘合IC芯片。