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    PROGRAMMABLE DEVICES WITH CURRENT-FACILITATED MIGRATION AND FABRICATION METHODS
    2.
    发明申请
    PROGRAMMABLE DEVICES WITH CURRENT-FACILITATED MIGRATION AND FABRICATION METHODS 有权

    公开(公告)号：US20170092373A1

    公开(公告)日：2017-03-30

    申请号：US14867331

    申请日：2015-09-28

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Suraj K. PATIL ,  Min-hwa CHI ,  Ajey P. JACOB

    IPC: G11C17/16 ,  H01L29/06 ,  H01L23/525 ,  H01L29/78

    CPC classification number: G11C17/16 ,  H01L23/5256 ,  H01L29/0673 ,  H01L29/785

    Abstract: Programmable devices and fabrication methods thereof are presented. The programmable devices include, for instance, a first electrode and a second electrode electrically connected by a link portion. The link portion includes one material of a metal material or a semiconductor material and the first and second electrodes includes the other material of the metal material or the semiconductor material. For example, the link portion facilitates programming the programmable device by applying a programming current between the first electrode and the second electrode to facilitate migration of the one material of the link portion towards at least one of the first or second electrodes. In one embodiment, the programming current is configured to heat the link portion to facilitate the migration of the one material of the link portion towards the at least one of the first or second electrodes.

    PROGRAMMABLE VIA DEVICES WITH METAL/SEMICONDUCTOR VIA LINKS AND FABRICATION METHODS THEREOF
    3.
    发明申请
    PROGRAMMABLE VIA DEVICES WITH METAL/SEMICONDUCTOR VIA LINKS AND FABRICATION METHODS THEREOF 有权

    公开(公告)号：US20170092583A1

    公开(公告)日：2017-03-30

    申请号：US14867341

    申请日：2015-09-28

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ajey P. JACOB ,  Suraj K. PATIL ,  Min-hwa CHI

    IPC: H01L23/525 ,  H01L23/522

    CPC classification number: H01L23/5256 ,  H01L23/5226

    Abstract: Programmable via devices and fabrication methods thereof are presented. The programmable via devices include, for instance, a first metal layer and a second metal layer electrically connected by a via link. The via link includes a semiconductor portion and a metal portion, where the via link facilitates programming of the programmable via device by applying a programming current through the via link to migrate materials between the semiconductor portion and the metal portion to facilitate a change of an electrical resistance of the via link. In one embodiment, the programming current facilitates formation of at least one gap region within the via link, the at least one gap region facilitating the change of the electrical resistance of the via link.

    MASK STRUCTURES AND METHODS OF MANUFACTURING
    4.
    发明申请
    MASK STRUCTURES AND METHODS OF MANUFACTURING 有权
    掩模结构和制造方法

    公开(公告)号：US20150212402A1

    公开(公告)日：2015-07-30

    申请号：US14168396

    申请日：2014-01-30

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Suraj K. PATIL ,  SherJang SINGH ,  Uzodinma OKOROANYANWU ,  Obert R. WOOD ,  Pawitter J.S. Mangat

    IPC: G03F1/24

    CPC classification number: G03F1/24

    Abstract: A lithography mask structure is provided, including: a substrate; at least one reflective layer over the substrate; and an absorber film stack over the at least one reflective layer, the absorber film stack including a plurality of first film layers of a first material and at least one second film layer of a second material. The second material is different from the first material, and the second film layer(s) is interleaved with the plurality of first film layers. In one embodiment, the total thickness of the absorber film stack is less than 50 nm. In another embodiment, the reflectivity of the absorber film stack is less than 2% for a pre-defined wavelength of EUV light. In a further embodiment, the second film layer(s) prevents the average crystallite size of the first film layers from exceeding the thickness of the first film layers.

    Abstract translation: 提供光刻掩模结构，包括：基板; 衬底上的至少一个反射层; 以及在所述至少一个反射层上的吸收膜叠层，所述吸收膜层包括多个第一材料的第一膜层和至少一个第二材料的第二膜层。 第二材料与第一材料不同，并且第二膜层与多个第一膜层交错。 在一个实施例中，吸收膜叠层的总厚度小于50nm。 在另一个实施例中，对于预定波长的EUV光，吸收膜叠层的反射率小于2％。 在另一实施例中，第二膜层防止第一膜层的平均微晶尺寸超过第一膜层的厚度。

    PROGRAMMABLE VIA DEVICES WITH METAL/SEMICONDUCTOR VIA LINKS AND FABRICATION METHODS THEREOF
    5.
    发明申请
    PROGRAMMABLE VIA DEVICES WITH METAL/SEMICONDUCTOR VIA LINKS AND FABRICATION METHODS THEREOF 审中-公开

    公开(公告)号：US20180033726A1

    公开(公告)日：2018-02-01

    申请号：US15724563

    申请日：2017-10-04

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ajey P. JACOB ,  Suraj K. PATIL ,  Min-hwa CHI

    IPC: H01L23/525 ,  H01L23/522

    CPC classification number: H01L23/5256 ,  H01L23/5226

    Abstract: Programmable via devices and fabrication methods thereof are presented. The programmable via devices include, for instance, a first metal layer and a second metal layer electrically connected by a via link. The via link includes a semiconductor portion and a metal portion, where the via link facilitates programming of the programmable via device by applying a programming current through the via link to migrate materials between the semiconductor portion and the metal portion to facilitate a change of an electrical resistance of the via link. In one embodiment, the programming current facilitates formation of at least one gap region within the via link, the at least one gap region facilitating the change of the electrical resistance of the via link.

    METHODS FOR FABRICATING PROGRAMMABLE DEVICES AND RELATED STRUCTURES
    6.
    发明申请
    METHODS FOR FABRICATING PROGRAMMABLE DEVICES AND RELATED STRUCTURES 有权
    用于制作可编程器件和相关结构的方法

    公开(公告)号：US20170062442A1

    公开(公告)日：2017-03-02

    申请号：US14842345

    申请日：2015-09-01

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Suraj K. PATIL ,  Ajey P. JACOB ,  Min-hwa CHI

    IPC: H01L27/112

    CPC classification number: H01L27/11206 ,  G11C13/0002 ,  G11C13/0009 ,  G11C13/0069 ,  G11C13/025 ,  G11C2013/008 ,  H01L23/5256 ,  H01L23/53276 ,  H01L27/112 ,  H01L29/0676 ,  H01L29/413

    Abstract: Methods and structures for programmable device fabrication are provided. The methods for fabricating a programmable device include, for example forming at least one via opening in a layer of the programmable device and providing a catalyzing material over a lower surface of the at least one via opening; forming a plurality of nanowires or nanotubes in the at least one via opening using the catalyzing material as a catalyst for the forming of the plurality of nanowires or nanotubes; and providing a dielectric material in the at least one via opening so that the dielectric material surrounds the plurality of nanowires or nanotubes. The programmable device may, in subsequent or separate programming steps, have programming of the programmable device made permanent via thermal oxidation of the dielectric material and the plurality of nanowires or nanotubes, leaving a non-conducting material behind in the at least one via opening.

    Abstract translation: 提供了可编程器件制造的方法和结构。 制造可编程装置的方法包括例如在可编程装置的层中形成至少一个通孔，并在至少一个通孔开口的下表面上提供催化材料; 在所述至少一个通孔开口中使用所述催化材料形成多个纳米线或纳米管作为用于形成所述多个纳米线或纳米管的催化剂; 以及在所述至少一个通孔开口中提供介电材料，使得所述电介质材料包围所述多个纳米线或纳米管。 可编程设备在随后或单独的编程步骤中可以通过介电材料和多个纳米线或纳米管的热氧化使可编程器件的编程永久化，在至少一个通孔开口之后留下非导电材料。

    SEMICONDUCTOR STRUCTURE WITH ANTI-EFUSE DEVICE
    9.
    发明申请
    SEMICONDUCTOR STRUCTURE WITH ANTI-EFUSE DEVICE 有权

    公开(公告)号：US20170125361A1

    公开(公告)日：2017-05-04

    申请号：US14926880

    申请日：2015-10-29

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Suraj K. PATIL ,  Min-hwa CHI ,  Ajey Poovannummoottil JACOB

    IPC: H01L23/62

    CPC classification number: H01L23/62 ,  H01L23/5252

    Abstract: A semiconductor structure includes a dielectric layer, a silicidable metal layer and an undoped filler material layer are used to create an anti-efuse device. The anti-efuse device may be situated in a dielectric layer of an interconnect structure for a semiconductor device or may be planar. Where part of an interconnect structure, the anti-efuse device may be realized by causing a current to flow therethrough while applying local heating. Where planar, the filler material may be situated between extensions of metal pads and metal atoms caused to move from the extensions to the filler material layer using a current flow and local heating.

    FABRICATION METHODS FOR MULTI-LAYER SEMICONDUCTOR STRUCTURES
    10.
    发明申请
    FABRICATION METHODS FOR MULTI-LAYER SEMICONDUCTOR STRUCTURES 有权
    多层半导体结构的制造方法

    公开(公告)号：US20160190014A1

    公开(公告)日：2016-06-30

    申请号：US14730614

    申请日：2015-06-04

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Suraj K. PATIL ,  Min-hwa CHI

    IPC: H01L21/8234 ,  H01L21/324 ,  H01L21/225 ,  H01L21/283

    CPC classification number: H01L21/823443 ,  H01L21/2253 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/283 ,  H01L21/285 ,  H01L21/28518 ,  H01L21/324 ,  H01L21/76889 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823821 ,  H01L21/823835 ,  H01L21/823842

    Abstract: Methods are provided for fabricating multi-layer semiconductor structures. The methods include, for example: providing a first layer and a second layer over a substrate, the first layer including a first metal and the second layer including a second metal, where the second layer is disposed over the first layer and the first metal and second metal are different metals; and annealing the first layer, the second layer, and the substrate to react at least a portion of the first metal of the first layer to form a first reacted layer and at least a portion of the second metal of the second layer to form a second reacted layer, where at least one of the first reacted layer or the second reacted layer includes at least one of a first metal silicide of the first metal or a second metal silicide of the second metal.

    Abstract translation: 提供了制造多层半导体结构的方法。 所述方法包括例如：在衬底上提供第一层和第二层，第一层包括第一金属，第二层包括第二金属，其中第二层设置在第一层和第一金属之上， 第二种金属是不同的金属; 以及退火所述第一层，所述第二层和所述衬底以使所述第一层的所述第一金属的至少一部分反应以形成第一反应层和所述第二层的所述第二金属的至少一部分，以形成第二层 其中第一反应层或第二反应层中的至少一个包含第一金属的第一金属硅化物或第二金属的第二金属硅化物中的至少一种。

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