公开(公告)号：US09252133B2

公开(公告)日：2016-02-02

申请号：US14487439

申请日：2014-09-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Christopher N. Collins ,  Mukta G. Farooq ,  Troy L. Graves-Abe ,  Joyce C. Liu ,  Gerd Pfeiffer ,  Thuy L. Tran-Quinn

IPC: H01L23/00 ,  H01L25/065 ,  H01L29/32 ,  H01L21/768 ,  H01L23/538

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L23/5384 ,  H01L29/32 ,  H01L2224/16225 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

Abstract: The formation of TSVs (through substrate vias) for 3D applications has proven to be defect dependent upon the type of starting semiconductor substrate employed. In addition to the initial formation of TSVs via Bosch processing, backside 3D wafer processing has also shown a defect dependency on substrate type. High yield of TSV formation can be achieved by utilizing a substrate that embodies bulk micro defects (BMD) at a density between 1e4/cc (particles per cubic centimeter) and 1e7/cc and having equivalent diameter less than 55 nm (nanometers).

Abstract translation: 已经证明用于3D应用的TSV（通过衬底通孔）的形成缺陷取决于所采用的起始半导体衬底的类型。 除了通过博世处理初始形成TSV之外，背面3D晶片处理也显示了对衬底类型的缺陷依赖性。 可以通过利用以1e4 / cc（每立方厘米颗粒）和1e7 / cc之间的密度并且具有小于55nm（纳米）的当量直径的体积微观缺陷（BMD）来实现高产率的TSV形成。

公开(公告)号：US09805977B1

公开(公告)日：2017-10-31

申请号：US15176598

申请日：2016-06-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vijay Sukumaran ,  Thuy L. Tran-Quinn ,  Jorge A. Lubguban ,  John J. Garant

IPC: H01L29/40 ,  H01L21/768 ,  H01L23/48 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/321

CPC classification number: H01L21/76898 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/32115 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76873 ,  H01L23/481

Abstract: One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include a front side and back side opposing the front side, the integrated circuit structure comprising: a through-silicon-via (TSV) at least partially within a dielectric layer extending away from the front side; a first metal adjacent to the TSV and within the dielectric layer, the first metal being substantially surrounded by a first seed layer; a conductive pad over the first metal and the TSV and extending away from the front side, wherein the conductive pad provides electrical connection between the TSV and the first metal and includes a second seed layer substantially surrounding a second metal, wherein the second seed layer separates the second metal from the first metal and the TSV.