公开(公告)号：US20160284540A1

公开(公告)日：2016-09-29

申请号：US14666787

申请日：2015-03-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shishir RAY ,  Yiqun LIU ,  Jin Ping LIU ,  Fabio D'ADDAMIO ,  Sandeep GAAN

IPC: H01L21/02 ,  H01L29/06 ,  H01L29/12

CPC classification number: H01L21/02181 ,  C23C16/308 ,  G11C11/22 ,  H01L21/02189 ,  H01L21/0234 ,  H01L21/28185 ,  H01L21/28194 ,  H01L29/513 ,  H01L29/517

Abstract: Provided is a semiconductor device that includes a semiconductor substrate and a 10 to 40 Å thick high-k dielectric layer that contains one or both of hafnium dioxide (HfO2) and zirconium dioxide (ZrO2). The high-k dielectric layer is disposed on the semiconductor substrate, and it contains at least some tetragonal phase HfO2 and/or tetragonal phase ZrO2. Also provided are methods for making the semiconductor device, and electronic devices that employ the semiconductor device.

Abstract translation: 提供了一种半导体器件，其包括半导体衬底和包含二氧化铪（HfO 2）和二氧化锆（ZrO 2）中的一种或两者的10至40厚的高k电介质层。 高k电介质层设置在半导体衬底上，并且其包含至少一些四方相HfO 2和/或四方相ZrO 2。 还提供了制造半导体器件的方法以及采用该半导体器件的电子器件。

公开(公告)号：US20150303115A1

公开(公告)日：2015-10-22

申请号：US14257899

申请日：2014-04-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yiqun LIU ,  Jeasung PARK ,  Chandra REDDY

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/28 ,  H01L27/088

CPC classification number: H01L21/82345 ,  H01L21/28088 ,  H01L27/088 ,  H01L29/4966 ,  H01L29/517

Abstract: Methodologies and resulting devices are provided for modified FET threshold voltages. Embodiments include: providing an active region of a transistor on a semiconductor substrate; depositing a workfunction metal on the active region; and modifying a threshold voltage of the transistor by treating the workfunction metal with oxygen. Other embodiments include: providing first and second active regions in a semiconductor substrate for first and second transistors, respectively; forming a first workfunction metal on the first active region; forming a second workfunction metal on the second active region; and modifying a first threshold voltage level of the first transistor, a second threshold voltage level of the second transistor, or a combination thereof by treating the first workfunction metal, second workfunction metal, or a combination thereof with oxygen, wherein the second threshold voltage level is greater than the first threshold voltage level.

Abstract translation: 为修改的FET阈值电压提供了方法和结果的器件。 实施例包括：在半导体衬底上提供晶体管的有源区; 在活性区域上沉积功函数金属; 以及通过用氧处理所述功函数金属来修改所述晶体管的阈值电压。 其他实施例包括：分别在用于第一和第二晶体管的半导体衬底中提供第一和第二有源区; 在所述第一活性区上形成第一功函数金属; 在所述第二活性区上形成第二功函数金属; 以及通过处理所述第一功函数金属，所述第二功函数金属或其与氧的组合来修改所述第一晶体管的第一阈值电压电平，所述第二晶体管的第二阈值电压电平或其组合，其中所述第二阈值电压电平 大于第一阈值电压电平。

公开(公告)号：US20150380409A1

公开(公告)日：2015-12-31

申请号：US14315885

申请日：2014-06-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mitsuhiro TOGO ,  Changyong XIAO ,  Yiqun LIU ,  Dina H. TRIYOSO ,  Rohit PAL

IPC: H01L27/092 ,  H01L21/321 ,  H01L21/265 ,  H01L21/8238 ,  H01L21/324

CPC classification number: H01L27/0922 ,  H01L21/26513 ,  H01L21/32115 ,  H01L21/324 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/845 ,  H01L27/0924 ,  H01L29/41791 ,  H01L29/49 ,  H01L29/4958 ,  H01L29/66545 ,  H01L29/66795

Abstract: A range of lowest, low and regular threshold voltages are provided to three p-type devices and three n-type devices co-fabricated on a same substrate. For the p-type devices, the range is achieved for the lowest using an additional thick layer of a p-type work function metal in a gate structure and oxidizing it, the low Vt is achieved with the thick p-type work function metal alone, and the regular Vt is achieved with a thinner layer of the p-type work function metal. For the n-type devices, the lowest Vt is achieved by implanting tantalum nitride with arsenic, argon, silicon or germanium and not adding any of the additional p-type work function metal in the gate structure, the low Vt is achieved by not adding the additional p-type work function metal, and the regular Vt is achieved with a thinnest layer of the p-type work function metal.

Abstract translation: 三个p型器件和在同一衬底上共同制造的三个n型器件提供了一个最低，低和规则阈值电压范围。 对于p型器件，使用栅极结构中的p型功函数金属的附加厚层并对其进行氧化来实现最低的范围，低Vt由厚的p型功函数金属单独实现 ，并且通过p型功函数金属的较薄层实现常规Vt。 对于n型器件，最低的Vt是通过用砷，氩，硅或锗注入氮化钽而不是在栅极结构中添加任何附加的p型功函数金属来实现的，低Vt是通过不添加 额外的p型功函数金属，而常规Vt是用最薄层的p型功函金属实现的。

公开(公告)号：US20160049400A1

公开(公告)日：2016-02-18

申请号：US14924486

申请日：2015-10-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mitsuhiro TOGO ,  Changyong XIAO ,  Yiqun LIU ,  Dina H. TRIYOSO ,  Rohit PAL

IPC: H01L27/092

CPC classification number: H01L27/0922 ,  H01L21/26513 ,  H01L21/32115 ,  H01L21/324 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/845 ,  H01L27/0924 ,  H01L29/41791 ,  H01L29/49 ,  H01L29/4958 ,  H01L29/66545 ,  H01L29/66795

Abstract: A range of lowest, low and regular threshold voltages are provided to three p-type devices and three n-type devices co-fabricated on a same substrate. For the p-type devices, the range is achieved for the lowest using an additional thick layer of a p-type work function metal in a gate structure and oxidizing it, the low Vt is achieved with the thick p-type work function metal alone, and the regular Vt is achieved with a thinner layer of the p-type work function metal. For the n-type devices, the lowest Vt is achieved by implanting tantalum nitride with arsenic, argon, silicon or germanium and not adding any of the additional p-type work function metal in the gate structure, the low Vt is achieved by not adding the additional p-type work function metal, and the regular Vt is achieved with a thinnest layer of the p-type work function metal.