公开(公告)号：US08963225B2

公开(公告)日：2015-02-24

申请号：US14024820

申请日：2013-09-12

Applicant: IMEC ,  GLOBALFOUNDRIES Inc.

Inventor： Benjamin Vincent ,  Geert Hellings ,  David Paul Brunco

IPC: H01L29/94 ,  H01L21/336

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/0257 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/785 ,  H01L29/7856

Abstract: The disclosure is related to a band engineered semiconductor device comprising a substrate, a protruding structure that is formed in a recess in the substrate and is extending above the recess having a buried portion and an extended portion, and wherein at least the extended portion comprises a semiconductor material having an inverted ‘V’ band gap profile with a band gap value increasing gradually from a first value at lateral edges of the structure to a second value, higher than the first value, in a center of the structure. The disclosure is also related to the method of manufacturing of such band engineered semiconductor device.

Abstract translation: 本发明涉及一种带状工程半导体器件，其包括衬底，突出结构，其形成在衬底中的凹部中并且在凹部上方延伸，具有掩埋部分和延伸部分，并且其中至少延伸部分包括 具有倒置“V”带隙分布的半导体材料，带隙值从该结构的横向边缘处的第一值逐渐增加到高于该结构的中心的第二值。 本发明还涉及这种带状工程半导体器件的制造方法。

公开(公告)号：US09029217B1

公开(公告)日：2015-05-12

申请号：US14592412

申请日：2015-01-08

Applicant: IMEC ,  GlobalFoundries Inc.

Inventor： Benjamin Vincent ,  Geert Hellings ,  David Paul Brunco

IPC: H01L21/336 ,  H01L29/94 ,  H01L29/66 ,  H01L29/161 ,  H01L21/02 ,  H01L29/10

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/0257 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/785 ,  H01L29/7856

Abstract: The disclosure is related to a band engineered semiconductor device comprising a substrate and a protruding structure that is formed in a recess in the substrate. The protruding structure extends above the recess and has a buried portion and an extended portion. At least the extended portion comprises a semiconductor material having an inverted ‘V’ band gap profile with a band gap value increasing gradually from a first value at lateral edges of the structure to a second value, higher than the first value, in a center of the structure. The disclosure is also related to the method of manufacturing of such a band engineered semiconductor device.

Abstract translation: 本公开涉及一种带状工程半导体器件，其包括衬底和形成在衬底中的凹部中的突出结构。 突出结构在凹部上方延伸并具有埋设部分和延伸部分。 至少延伸部分包括具有倒置的“V”带隙轮廓的半导体材料，带隙值从结构的横向边缘处的第一值逐渐增加到高于第一值的第二值，高于第一值 结构。 本公开还涉及制造这种带状工程半导体器件的方法。

公开(公告)号：US20150126010A1

公开(公告)日：2015-05-07

申请号：US14592412

申请日：2015-01-08

Applicant: IMEC ,  GLOBALFOUNDRIES INC.

Inventor： Benjamin Vincent ,  Geert Hellings ,  David Paul Brunco

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/10 ,  H01L29/161

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/0257 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/785 ,  H01L29/7856

Abstract: The disclosure is related to a band engineered semiconductor device comprising a substrate and a protruding structure that is formed in a recess in the substrate. The protruding structure extends above the recess and has a buried portion and an extended portion. At least the extended portion comprises a semiconductor material having an inverted ‘V’ band gap profile with a band gap value increasing gradually from a first value at lateral edges of the structure to a second value, higher than the first value, in a center of the structure. The disclosure is also related to the method of manufacturing of such a band engineered semiconductor device.

Abstract translation: 本公开涉及一种带状工程半导体器件，其包括衬底和形成在衬底中的凹部中的突出结构。 突出结构在凹部上方延伸并具有埋设部分和延伸部分。 至少延伸部分包括具有倒置的“V”带隙轮廓的半导体材料，带隙值从结构的横向边缘处的第一值逐渐增加到高于第一值的第二值，高于第一值 结构。 本公开还涉及制造这种带状工程半导体器件的方法。

公开(公告)号：US20180145079A1

公开(公告)日：2018-05-24

申请号：US15875609

申请日：2018-01-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： David Paul Brunco ,  Jeffrey Bowman Johnson

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/225 ,  H01L21/265 ,  H01L21/762 ,  H01L21/02 ,  H01L29/167 ,  H01L29/10

CPC classification number: H01L27/0924 ,  H01L21/02529 ,  H01L21/22 ,  H01L21/2251 ,  H01L21/26513 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/823892 ,  H01L29/1033 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/167

Abstract: Generally, in one embodiment, the present disclosure is directed to a method for forming a transistor. The method includes: implanting a substrate to form at least one of an n and p doped region; depositing an epitaxial semiconductor layer over the substrate; forming trenches through the epitaxial layer and partially through at least one of an n and p doped region; forming dielectric isolation regions in the trenches; forming a fin in an upper portion of the epitaxial semiconductor layer by partially recessing the dielectric isolation regions; forming a gate dielectric adjacent at least two surfaces of the fin; and diffusing dopant from at least one of the n and p doped regions at least partially into the epitaxial semiconductor layer to form a diffusion doped transition region adjacent a bottom portion of the fin.

公开(公告)号：US20150318169A1

公开(公告)日：2015-11-05

申请号：US14267634

申请日：2014-05-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yi Qi ,  Ajey Poovannummoottil Jacob ,  Jody A. Fronheiser ,  Murat Kerem Akarvardar ,  David Paul Brunco

IPC: H01L21/02 ,  H01L29/161 ,  H01L29/66

CPC classification number: H01L29/161 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/0262 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7848

Abstract: One illustrative method disclosed herein includes, among other things, forming a fin in a semiconductor substrate and performing an epitaxial deposition process using a combination of silane (SiH4), dichlorosilane (SiH2Cl2), germane (GeH4) and a carrier gas to form an epi semiconductor material around the fin, wherein the flow rate of dichlorosilane used during the epitaxial deposition process is equal to 10-90% of the combined flow rate of silane and dichlorosilane.

Abstract translation: 本文公开的一种说明性方法包括在半导体衬底中形成翅片并使用硅烷（SiH 4），二氯硅烷（SiH 2 Cl 2），锗烷（GeH 4）和载气的组合进行外延沉积工艺以形成外延 散热片周围的半导体材料，其中在外延沉积工艺期间使用的二氯硅烷的流速等于硅烷和二氯硅烷的组合流速的10-90％。

公开(公告)号：US10014409B1

公开(公告)日：2018-07-03

申请号：US15393400

申请日：2016-12-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xusheng Wu ,  David Paul Brunco

IPC: H01L29/732 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/40 ,  H01L29/08 ,  H01L29/06

Abstract: A vertical fin field effect transistor includes a semiconductor fin disposed over a well region and a gate conductor layer disposed over a sidewall of the fin, and extending laterally over a top surface of the well region adjacent to the fin. The extension of the gate conductor over the bottom source/drain effectively increases the channel length of the vertical FinFET device independent of the fin height. A bottom source/drain region is laterally adjacent to the well region such that the portion of the well region covered by the laterally extended gate stack is between the bottom source/drain region and the portion of the well region immediately under the fin. A top source/drain region is located above the fin. The device is operated in circuits by use of electrical contacts to the bottom source/drain, the gate conductor, and the top source/drain.

公开(公告)号：US20170250183A1

公开(公告)日：2017-08-31

申请号：US15053984

申请日：2016-02-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： David Paul Brunco

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/306 ,  H01L29/06 ,  H01L29/167 ,  H01L29/10 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/265

CPC classification number: H01L27/0924 ,  H01L21/02532 ,  H01L21/26513 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/1095 ,  H01L29/167

Abstract: At least one method, apparatus and system disclosed involves forming a finFET device having silicon and silicon germanium fins. The method includes: forming an n-doped and a p-doped region in a semiconductor wafer; forming a layer of silicon above both the those regions; removing a portion of the silicon layer above the p-doped region to create a first recess; forming a layer of silicon germanium in the first recess; etching away at least a portion of the silicon layer and the underlying p-doped region; etching away at least a portion of the silicon germanium layer and the underlying n-doped region; forming fins from the unetched silicon and silicon germanium layers; and forming a shallow trench isolation dielectric in the etched away portion of the silicon layer and the underlying p-doped region and in the etched away portion of the silicon germanium layer and the underlying n-doped region.

公开(公告)号：US20180102291A1

公开(公告)日：2018-04-12

申请号：US15288503

申请日：2016-10-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： David Paul Brunco ,  Daniel Jaeger

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/02

CPC classification number: H01L21/823431 ,  H01L21/02129 ,  H01L21/823481 ,  H01L27/0886

Abstract: Generally, the present disclosure is directed to a method for forming a FinFET device that may be used in designs that include both tight and relaxed fin pitches. The method for forming the fins includes: forming a first layer of doped silicate glass above a semiconductor wafer and within a plurality of recesses located adjacent the fins; forming a first layer of nitride above the first doped silicate glass layer; and forming a conformal oxide layer above the first nitride layer, substantially filling relatively narrow recesses between fins having a tight pitch and lining relatively wide recesses between fins having a relaxed pitch.

公开(公告)号：US09929159B2

公开(公告)日：2018-03-27

申请号：US15053984

申请日：2016-02-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： David Paul Brunco

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/306 ,  H01L21/265 ,  H01L29/167 ,  H01L29/10 ,  H01L21/762 ,  H01L29/06

CPC classification number: H01L27/0924 ,  H01L21/02532 ,  H01L21/26513 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/1095 ,  H01L29/167

Abstract: At least one method, apparatus and system disclosed involves forming a finFET device having silicon and silicon germanium fins. The method includes: forming an n-doped and a p-doped region in a semiconductor wafer; forming a layer of silicon above both the those regions; removing a portion of the silicon layer above the p-doped region to create a first recess; forming a layer of silicon germanium in the first recess; etching away at least a portion of the silicon layer and the underlying p-doped region; etching away at least a portion of the silicon germanium layer and the underlying n-doped region; forming fins from the unetched silicon and silicon germanium layers; and forming a shallow trench isolation dielectric in the etched away portion of the silicon layer and the underlying p-doped region and in the etched away portion of the silicon germanium layer and the underlying n-doped region.

公开(公告)号：US20180019241A1

公开(公告)日：2018-01-18

申请号：US15208495

申请日：2016-07-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： David Paul Brunco ,  Jeffrey Bowman Johnson

IPC: H01L27/092 ,  H01L29/10 ,  H01L21/225 ,  H01L21/02 ,  H01L21/762 ,  H01L21/265 ,  H01L29/167 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L21/02529 ,  H01L21/2251 ,  H01L21/26513 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/823892 ,  H01L29/1033 ,  H01L29/1083 ,  H01L29/167

Abstract: Generally, in one embodiment, the present disclosure is directed to a method for forming a transistor. The method includes: implanting a substrate to form at least one of an n and p doped region; depositing an epitaxial semiconductor layer over the substrate; forming trenches through the epitaxial layer and partially through at least one of an n and p doped region; forming dielectric isolation regions in the trenches; forming a fin in an upper portion of the epitaxial semiconductor layer by partially recessing the dielectric isolation regions; forming a gate dielectric adjacent at least two surfaces of the fin; and diffusing dopant from at least one of the n and p doped regions at least partially into the epitaxial semiconductor layer to form a diffusion doped transition region adjacent a bottom portion of the fin.