公开(公告)号：US09892054B2

公开(公告)日：2018-02-13

申请号：US14877629

申请日：2015-10-07

Applicant: GOOGLE INC.

Inventor： Shinye Shiu

IPC: G06F12/1009 ,  G06F3/06 ,  G06F12/0891 ,  G06F12/12 ,  G06F12/0897 ,  G06F12/1027 ,  G06F12/0802 ,  G06F12/0864 ,  G06F12/121

CPC classification number: G06F12/1009 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0638 ,  G06F3/0653 ,  G06F3/0656 ,  G06F3/0673 ,  G06F3/0683 ,  G06F12/0802 ,  G06F12/0864 ,  G06F12/0891 ,  G06F12/0897 ,  G06F12/1027 ,  G06F12/12 ,  G06F12/121 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/401 ,  G06F2212/502 ,  G06F2212/601 ,  G06F2212/604 ,  G06F2212/65 ,  G06F2212/68 ,  G06F2212/683 ,  Y02D10/13 ,  Y02D10/22

Abstract: A method and apparatus are disclosed to monitor system performance and dynamically update memory subsystem settings using software to optimize system performance and power consumption. In an example embodiment, the apparatus monitors a software application's cache performance and provides the software application the cache performance data. The software application, which has a higher-level/macro view of the overall system and better determination of its future requests, analyzes the performance data to determine more optimal memory sub-system settings. The software application provides the system more optimal settings to implement in the memory component to improve the memory and overall system performance and efficiency.

公开(公告)号：US09864541B2

公开(公告)日：2018-01-09

申请号：US15043023

申请日：2016-02-12

Applicant: GOOGLE INC.

Inventor： Vyacheslav Vladimirovich Malyugin ,  Luigi Semenzato ,  Choon Ping Chng ,  Santhosh Rao ,  Shinye Shiu

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F3/06 ,  G06F12/02 ,  G06F12/0888 ,  G06F12/0804 ,  G06F12/0871

CPC classification number: G06F3/064 ,  G06F3/0604 ,  G06F3/0631 ,  G06F3/0673 ,  G06F12/023 ,  G06F12/0804 ,  G06F12/0871 ,  G06F12/0888 ,  G06F2003/0691 ,  G06F2212/401 ,  Y02B70/30 ,  Y02D10/13

Abstract: Provided are methods and systems for memory decompression using a hardware decompressor that minimizes or eliminates the involvement of software. Custom decompression hardware is added to the memory subsystem, where the decompression hardware handles read accesses caused by, for example, cache misses or requests from devices to compressed memory blocks, by reading a compressed block, decompressing it into an internal buffer, and returning the requested portion of the block. The custom hardware is designed to determine if the block is compressed, and determine the parameters of compression, by checking unused high bits of the physical address of the access. This allows compression to be implemented without additional metadata, because the necessary metadata can be stored in unused bits in the existing page table structures.

公开(公告)号：US10089239B2

公开(公告)日：2018-10-02

申请号：US15165839

申请日：2016-05-26

Applicant: GOOGLE INC.

Inventor： Allan D. Knies ,  Shinye Shiu ,  Chih-Chung Chang ,  Vyacheslav Vladimirovich Malyugin ,  Santhosh Rao

IPC: G06F12/08 ,  G06F12/10 ,  G06F12/12 ,  G06F12/0893 ,  G06F12/0891 ,  G06F12/1045 ,  G06F12/0888 ,  G06F12/084 ,  G06F12/127

Abstract: Provided are methods, systems, and apparatus for managing and controlling memory caches, in particular, system level caches outside of those closest to the CPU. The processes and representative hardware structures that implement the processes are designed to allow for detailed control over the behavior of such system level caches. Caching policies are developed based on policy identifiers, where a policy identifier corresponds to a collection of parameters that control the behavior of a set of cache management structures. For a given cache, one policy identifier is stored in each line of the cache.

公开(公告)号：US09740631B2

公开(公告)日：2017-08-22

申请号：US14877484

申请日：2015-10-07

Applicant: GOOGLE INC.

Inventor： Shinye Shiu

IPC: G06F12/10 ,  G06F12/1009 ,  G06F3/06 ,  G06F12/0891 ,  G06F12/12 ,  G06F12/0897 ,  G06F12/1027 ,  G06F12/0802 ,  G06F12/0864 ,  G06F12/121

CPC classification number: G06F12/1009 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0638 ,  G06F3/0653 ,  G06F3/0656 ,  G06F3/0673 ,  G06F3/0683 ,  G06F12/0802 ,  G06F12/0864 ,  G06F12/0891 ,  G06F12/0897 ,  G06F12/1027 ,  G06F12/12 ,  G06F12/121 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/401 ,  G06F2212/502 ,  G06F2212/601 ,  G06F2212/604 ,  G06F2212/65 ,  G06F2212/68 ,  G06F2212/683 ,  Y02D10/13 ,  Y02D10/22

Abstract: Provided are methods and systems for managing memory using a hardware-based page filter designed to distinguish between active and inactive pages (“hot” and “cold” pages, respectively) so that inactive pages can be compressed prior to the occurrence of a page fault. The methods and systems are designed to achieve, among other things, lower cost, longer battery life, and faster user response. Whereas existing approaches for memory management are based on pixel or frame buffer compression, the methods and systems provided focus on the CPU's program (e.g., generic data structure). Focusing on hardware-accelerated memory compression to offload CPU translates higher power efficiency (e.g., ASIC is approximately 100× lower power than CPU) and higher performance (e.g., ASIC is approximately 10× faster than CPU), and also allows for hardware-assisted memory management to offload OS/kernel, which significantly increases response time.

公开(公告)号：US09785571B2

公开(公告)日：2017-10-10

申请号：US14877523

申请日：2015-10-07

Applicant: GOOGLE INC.

Inventor： Shinye Shiu

IPC: G06F12/10 ,  G06F12/1009 ,  G06F3/06 ,  G06F12/0891 ,  G06F12/12 ,  G06F12/0897 ,  G06F12/1027 ,  G06F12/0802 ,  G06F12/0864 ,  G06F12/121

CPC classification number: G06F12/1009 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0638 ,  G06F3/0653 ,  G06F3/0656 ,  G06F3/0673 ,  G06F3/0683 ,  G06F12/0802 ,  G06F12/0864 ,  G06F12/0891 ,  G06F12/0897 ,  G06F12/1027 ,  G06F12/12 ,  G06F12/121 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/401 ,  G06F2212/502 ,  G06F2212/601 ,  G06F2212/604 ,  G06F2212/65 ,  G06F2212/68 ,  G06F2212/683 ,  Y02D10/13 ,  Y02D10/22

Abstract: Provided are methods and systems for de-duplicating cache lines in physical memory by detecting cache line data patterns and building a link-list between multiple physical addresses and their common data value. In this manner, the methods and systems are applied to achieve de-duplication of an on-chip cache. A cache line filter includes one table that defines the most commonly duplicated content patterns and a second table that saves pattern numbers from the first table and the physical address for she duplicated cache line. Since a cache line duplicate can be detected during a write operation, each write can involve table lookup and comparison. If there is a hit in the table, only the address is saved instead of the entire data string.