公开(公告)号：US10599443B2

公开(公告)日：2020-03-24

申请号：US15787667

申请日：2017-10-18

申请人： GSI Technology, Inc.

发明人： Young-Nam Oh ,  Soon Kyu Park ,  Jae Hyeong Kim

IPC分类号： G11C5/14 ,  G06F9/4401 ,  G11C7/22 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4097 ,  G06F1/10 ,  G06F1/26

摘要： A method of operating a clock frequency detected control-i/o buffer enable circuit in a semiconductor device uses control I/O buffer enable circuitry and/or features of saving power in standby mode. The method may provide low standby power consumption, such as providing low standby power consumption in high-speed synchronous SRAM and RLDRAM devices.

公开(公告)号：US09494647B1

公开(公告)日：2016-11-15

申请号：US14588368

申请日：2014-12-31

申请人： GSI TECHNOLOGY, INC.

发明人： Patrick T. Chuang ,  Mu-Hsiang Huang ,  Jae Hyeong Kim

IPC分类号： G11C7/06 ,  G11C16/26 ,  G11C11/4091 ,  G01R31/317

CPC分类号： G11C11/4091 ,  G11C7/065 ,  G11C7/067 ,  G11C7/1006 ,  G11C7/1057 ,  G11C7/1084 ,  G11C16/26

摘要： Systems and methods of data inversion, circuitry, detection and/or schemes are disclosed. According to illustrative implementations, exemplary circuitry may include static detection or detection circuitry such as those involving static current sources to detect a threshold for data inversion, pre-conditioning of detection circuitry, and/or active detection circuitry or schemes. In some implementations, exemplary memory or data inversion circuitry may comprise a transistor array, a bias generator, and a sense amplifier, wherein the transistor array may comprise at least one pair of transistor circuits arranged so that an output of the transistor array is provided as a sum or function of signal/current outputs of at least some of the transistor circuits in the array. As set forth, various systems, methods and circuitry herein may posses only a 3 static gate delay, such that very high speed and/or fast flow-through is achieved.

摘要翻译： 公开了数据反转，电路，检测和/或方案的系统和方法。 根据说明性实现，示例性电路可以包括静态检测或检测电路，例如涉及用于检测用于数据反转的阈值，检测电路的预处理和/或主动检测电路或方案的静态电流源的静态检测或检测电路。 在一些实现中，示例性存储器或数据反转电路可以包括晶体管阵列，偏置发生器和读出放大器，其中晶体管阵列可以包括至少一对晶体管电路，其布置成使得晶体管阵列的输出被提供为 阵列中的至少一些晶体管电路的信号/电流输出的和或函数。 如上所述，本文中的各种系统，方法和电路可以仅具有3个静态门延迟，使得实现非常高的速度和/或快速流通。

公开(公告)号：US09804856B2

公开(公告)日：2017-10-31

申请号：US14996870

申请日：2016-01-15

申请人： GSI TECHNOLOGY, INC.

发明人： Young-Nam Oh ,  Soon Kyu Park ,  Jae Hyeong Kim

IPC分类号： G06F9/44 ,  G11C7/22 ,  G11C5/14 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4097 ,  G06F1/10 ,  G06F1/26

CPC分类号： G06F9/4403 ,  G06F1/10 ,  G06F1/26 ,  G11C5/148 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4097 ,  G11C2207/2227

摘要： A method of operating a clock frequency detected control I/O buffer enable circuitry and/or features of saving power. In illustrative implementations, the method may be directed to providing low standby power consumption, such as providing low standby power consumption in high-speed synchronous SRAM and RLDRAM devices.

公开(公告)号：US09356611B1

公开(公告)日：2016-05-31

申请号：US14607068

申请日：2015-01-27

申请人： GSI Technology, Inc.

发明人： Jyn-Bang Shyu ,  Yoshinori Sato ,  Jae Hyeong Kim ,  Lee-Lean Shu

IPC分类号： H03L7/06 ,  H03L7/085

CPC分类号： H03L7/085 ,  H03L7/0814 ,  H03L7/0816 ,  H03L7/0818 ,  H03L7/087 ,  H03L7/095

摘要： Systems and methods associated with control of clock signals are disclosed. In one exemplary implementation, there is provided a delay-lock-loop (DLL) and/or a delay/phase detection circuit. Moreover, such circuit may comprise digital phase detection circuitry, digital delay control circuitry, analog phase detection circuitry, and analog delay control circuitry. Implementations may include configurations that prevent transition back to the unlocked state due to jitter or noise.

公开(公告)号：US09018992B1

公开(公告)日：2015-04-28

申请号：US14161623

申请日：2014-01-22

申请人： GSI Technology, Inc.

发明人： Jyn-Bang Shyu ,  Yoshinori Sato ,  Jae Hyeong Kim ,  Lee-Lean Shu

IPC分类号： H03L7/06 ,  H03L7/095

CPC分类号： H03L7/095 ,  H03L7/0814 ,  H03L7/0816

摘要： Systems and methods associated with control of clock signals are disclosed. In one exemplary implementation, there is provided a delay-lock-loop (DLL) and/or a delay/phase detection circuit. Moreover, such circuit may comprise digital phase detection circuitry, digital delay control circuitry, analog phase detection circuitry, and analog delay control circuitry. Implementations may include configurations that prevent transition back to the unlocked state due to jitter or noise.

摘要翻译： 公开了与控制时钟信号相关联的系统和方法。 在一个示例性实现中，提供了延迟锁定环（DLL）和/或延迟/相位检测电路。 此外，这种电路可以包括数字相位检测电路，数字延迟控制电路，模拟相位检测电路和模拟延迟控制电路。 实现可以包括由于抖动或噪声而防止转换回解锁状态的配置。

公开(公告)号：US08575982B1

公开(公告)日：2013-11-05

申请号：US13789678

申请日：2013-03-08

申请人： GSI Technology, Inc.

发明人： Jae Hyeong Kim ,  Jyn-Bang Shyu ,  Lee-Lean Shu

IPC分类号： H03L7/06

CPC分类号： H03L7/0812 ,  H03L7/10

摘要： The present disclosure relates to systems and methods of noise reduction and/or power saving. According to one or more illustrative implementations, for example, innovations consistent with delay lines in clock/timing circuits such as Delay-Lock-Loop (DLL) and/or Duty Cycle Correction (DCC) circuits are disclosed.

摘要翻译： 本公开涉及降低噪声和/或省电的系统和方法。 根据一个或多个说明性实现，例如，公开了与诸如延迟锁定环（DLL）和/或占空比校正（DCC）电路的时钟/定时电路中的延迟线一致的创新。