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16 条记录 (耗时 0.026 秒)

    Transmit-buffer management for priority-based flow control
    1.
    发明授权
    Transmit-buffer management for priority-based flow control 有权
    发送缓冲区管理，用于基于优先级的流量控制

    公开(公告)号：US08520522B1

    公开(公告)日：2013-08-27

    申请号：US12905696

    申请日：2010-10-15

    申请人： Gary Goldman ,  Paul Kim ,  Chang-Hong Wu

    发明人： Gary Goldman ,  Paul Kim ,  Chang-Hong Wu

    IPC分类号： H04L12/26

    CPC分类号： H04L47/26 ,  H04L47/29 ,  H04L47/30

    摘要： A network device operating in operating in a Priority Flow Control (PFC) mode receives a stream of packets for outputting on a particular port, assigns each packet in the stream of packets to one of multiple buffer queues associated with the port, and generates, based on the assigning, packet counts for the multiple buffer queues. The network device aggregates the packet counts for a group of particular buffer queues, of the multiple buffer queues, that are not subject to a PFC restriction, to create an unrestricted aggregated count. The network device determines whether the unrestricted aggregated count exceeds a flow-control threshold for the group of particular buffer queues and sends, to an upstream queue scheduler, a flow control signal when the unrestricted aggregated count exceeds a flow-control threshold.

    摘要翻译： 以优先级流量控制（PFC）模式操作的网络设备接收用于在特定端口上输出的分组流，将分组流中的每个分组分配给与端口相关联的多个缓冲器队列之一，并基于 对多个缓冲区队列的分配计数。 网络设备聚合不受PFC限制的多个缓冲区队列的一组特定缓冲队列的分组计数，以创建无限制的聚合计数。 网络设备确定无限制聚合计数是否超过特定缓冲队列组的流量控制阈值，并且当无限制聚合计数超过流量控制阈值时，向上游队列调度器发送流控制信号。

    Digital bit insertion for clock recovery
    2.
    发明授权
    Digital bit insertion for clock recovery 有权
    数字位插入用于时钟恢复

    公开(公告)号：US09237003B1

    公开(公告)日：2016-01-12

    申请号：US13204391

    申请日：2011-08-05

    申请人： David P. Chengson ,  Chang-Hong Wu

    发明人： David P. Chengson ,  Chang-Hong Wu

    IPC分类号： H04L7/033

    CPC分类号： H04L7/033 ,  H04L25/49

    摘要： In general, techniques are described that insert one or more bits into a digital bit stream to maintain an overall transition density in the digital bit stream. Maintaining the overall transition density facilitates the generation of a recovered clock by a phase-locked loop (PLL) circuit of a receiver. For example, when a data transition ratio for a portion of the digital bit stream is less than a desired data transition ratio, the techniques insert additional bits to increase the overall transition density of the digital bit stream.

    摘要翻译： 通常，描述了将一个或多个比特插入到数字比特流中以保持数字比特流中的总体转移密度的技术。 维持整个转换密度有助于通过接收机的锁相环（PLL）电路产生恢复的时钟。 例如，当数字比特流的一部分的数据转换比小于期望的数据转换比时，该技术插入附加比特以增加数字比特流的整体转换密度。

    Hybrid weighted round robin (WRR) traffic scheduling
    3.
    发明授权
    Hybrid weighted round robin (WRR) traffic scheduling 有权
    混合加权轮询（WRR）流量调度

    公开(公告)号：US08462802B2

    公开(公告)日：2013-06-11

    申请号：US12880403

    申请日：2010-09-13

    申请人： Aibing Zhou ,  John Johnson ,  Chang-Hong Wu ,  David J. Ofelt

    发明人： Aibing Zhou ,  John Johnson ,  Chang-Hong Wu ,  David J. Ofelt

    IPC分类号： H04L12/54

    CPC分类号： H04L47/522

    摘要： A network device receives traffic associated with a network of intermediate network devices and user devices, classifies the received traffic, and allocates the classified traffic to traffic queues. The network device also schedules particular queued traffic, provided in the traffic queues and bound for particular intermediate network devices, using a hybrid weighted round robin (WRR) scheduler where the hybrid WRR scheduler schedules the particular queued traffic according to one of a 1-level WRR schedule, a 1.5 level WRR schedule, or a 2-level WRR schedule. The network device further provides the particular queued traffic to the particular intermediate network devices based on the scheduling of the hybrid WRR scheduler.

    摘要翻译： 网络设备接收与中间网络设备和用户设备的网络相关联的流量，对接收到的流量进行分类，并将分类流量分配给业务队列。 网络设备还使用混合加权轮询（WRR）调度器来调度在业务队列中提供并且被绑定到特定中间网络设备的特定排队的业务，其中混合WRR调度器根据1级的其中一个级别调度特定的排队业务 WRR表，1.5级WRR表，或2级WRR表。 网络设备还基于混合WRR调度器的调度进一步向特定的中间网络设备提供特定的排队流量。

    LOW LATENCY SERIAL MEMORY INTERFACE
    4.
    发明申请
    LOW LATENCY SERIAL MEMORY INTERFACE 有权
    低延迟串行存储器接口

    公开(公告)号：US20110161544A1

    公开(公告)日：2011-06-30

    申请号：US12648373

    申请日：2009-12-29

    申请人： David P. Chengson ,  Chang-Hong Wu

    发明人： David P. Chengson ,  Chang-Hong Wu

    IPC分类号： G06F13/14 ,  G06F13/00 ,  G06F1/04

    CPC分类号： G06F13/1689 ,  H04L25/03866 ,  H04L25/06

    摘要： A device applies synchronous clocking across a first component and a second component of the device, and designates a particular serial link, from a group of serial links, as a master serial link. The device also designates the remaining serial links as slave serial links, provides, via the master serial link, an encoded data stream, and provides, via the slave serial links, un-encoded and scrambled data streams.

    摘要翻译： 一个设备跨设备的第一个组件和第二个组件应用同步时钟，并从一组串行链路指定一个特定的串行链路作为主串行链路。 该设备还将剩余的串行链路指定为从串行链路，通过主串行链路提供编码数据流，并通过从串行链路提供未编码和加扰的数据流。

    Low latency serial memory interface
    6.
    发明授权
    Low latency serial memory interface 有权
    低延迟串行存储器接口

    公开(公告)号：US08452908B2

    公开(公告)日：2013-05-28

    申请号：US12648373

    申请日：2009-12-29

    申请人： David P. Chengson ,  Chang-Hong Wu

    发明人： David P. Chengson ,  Chang-Hong Wu

    IPC分类号： G06F13/14 ,  G06F3/00 ,  G06F5/00 ,  G06F1/04 ,  G06F1/12 ,  G06F5/06

    CPC分类号： G06F13/1689 ,  H04L25/03866 ,  H04L25/06

    摘要： A device applies synchronous clocking across a first component and a second component of the device, and designates a particular serial link, from a group of serial links, as a master serial link. The device also designates the remaining serial links as slave serial links, provides, via the master serial link, an encoded data stream, and provides, via the slave serial links, un-encoded and scrambled data streams.

    摘要翻译： 一个设备跨设备的第一个组件和第二个组件应用同步时钟，并从一组串行链路指定一个特定的串行链路作为主串行链路。 该设备还将剩余的串行链路指定为从串行链路，通过主串行链路提供编码数据流，并通过从串行链路提供未编码和加扰的数据流。

    Clock controller for controlling the switching to redundant clock signal without producing glitches by delaying the redundant clock signal to match a phase of primary clock signal
    7.
    发明授权
    Clock controller for controlling the switching to redundant clock signal without producing glitches by delaying the redundant clock signal to match a phase of primary clock signal 有权
    时钟控制器，用于通过延迟冗余时钟信号来匹配主时钟信号的相位来控制切换到冗余时钟信号而不产生毛刺

    公开(公告)号：US06675307B1

    公开(公告)日：2004-01-06

    申请号：US09536886

    申请日：2000-03-28

    申请人： Ross S. Heitkamp ,  Chang-Hong Wu

    发明人： Ross S. Heitkamp ,  Chang-Hong Wu

    IPC分类号： G06F112

    CPC分类号： G06F1/12

    摘要： A system and method for controlling clocking signals including a clock controller that includes a first input operable to receive a first clock signal having a first frequency, a second input operable to receive a second clock having a same frequency as the first clock signal but of arbitrary phase, a first output and a variable delay line coupling the first clock signal received at the first input to the first output. The first output is operable to couple a delayed version of the first clock signal to the receiving device. The clock controller includes a comparator receiving as an input the first and the second clock signals from the first and second inputs and providing as an output to the variable delay line a control signal for adjusting a delay in the first clock signal so as to match a phase of the second clock signal received at the receiving device.

    摘要翻译： 一种用于控制时钟信号的系统和方法，包括时钟控制器，时钟控制器包括可操作以接收具有第一频率的第一时钟信号的第一输入端，可操作以接收具有与第一时钟信号相同频率但任意的第二时钟的第二时钟的第二输入 相位，第一输出和可变延迟线，将在第一输入处接收的第一时钟信号耦合到第一输出。 第一输出可操作以将第一时钟信号的延迟版本耦合到接收装置。 时钟控制器包括一个比较器，用于从第一和第二输入端接收第一和第二时钟信号作为输入，并向可变延迟线提供用于调整第一时钟信号延迟的控制信号，以便匹配一个 在接收设备处接收的第二时钟信号的相位。