公开(公告)号：US5933609A

公开(公告)日：1999-08-03

申请号：US629015

申请日：1996-04-08

申请人： Gary Walker ,  Franklyn H. Story ,  David Evoy ,  Michael Crews ,  Peter Chambers

发明人： Gary Walker ,  Franklyn H. Story ,  David Evoy ,  Michael Crews ,  Peter Chambers

IPC分类号： G06F3/00 ,  G06F1/16 ,  G06F13/40 ,  G06F13/00

CPC分类号： G06F13/4081 ,  G06F1/1632

摘要： A portable computer and corresponding docking station, where the portable computer may be inserted into or removed from the docking station without concern relating to the state of either the portable computer or of the docking station. The hot docking sequence is performed by establishing a direct connection to the primary PCI bus without the risk of any possible system damage, file damage, or data loss. This can be accomplished even while the portable computer system is powered on and is actively running. The present invention prevents glitches from occurring in pre-existing pins and adds four new pins to implement this novel hot docking sequence. Furthermore, hot undocking can be readily performed as well by basically reversing the docking sequence.

摘要翻译： 一种便携式计算机和相应的对接站，其中便携式计算机可以插入或从对接站移除，而不用担心便携式计算机或坞站的状态。 通过建立与主PCI总线的直接连接而不会有任何可能的系统损坏，文件损坏或数据丢失的风险来执行热对接序列。 即使在便携式计算机系统通电并且正在运行的情况下也可以实现这一点。 本发明可以防止在先前存在的引脚中发生毛刺，并增加四个新引脚来实现这种新的热对接序列。 此外，通过基本上逆转对接序列，也可以容易地进行热脱离。

公开(公告)号：US5809333A

公开(公告)日：1998-09-15

申请号：US627988

申请日：1996-04-08

申请人： Franklyn H. Story ,  David R. Evoy ,  Peter Chambers ,  Lonnie Goff

发明人： Franklyn H. Story ,  David R. Evoy ,  Peter Chambers ,  Lonnie Goff

IPC分类号： G06F13/28 ,  G06F9/00 ,  G06F13/00

CPC分类号： G06F13/28

摘要： The present invention is a desktop personal computer (PC) system having peripheral device bus mastering. The system has four main elements: a Direct Memory Access (DMA) controller, a hardware state machine, a bus controller, and a device controller. The device controller may be an IDE hard disk controller which is able to generate long streams of data in an intermittent fashion wherein any single stream of data is targeted to a number of different host memory locations. The device controller may also be an ECP parallel port controller which interfaces with a number of different peripheral devices over a parallel bus wherein each peripheral device appears to the system as a separate and independent data path.

摘要翻译： 本发明是具有外围设备总线母盘的台式个人计算机（PC）系统。 该系统有四个主要元件：直接存储器访问（DMA）控制器，硬件状态机，总线控制器和设备控制器。 设备控制器可以是IDE硬盘控制器，其能够以间歇方式产生长数据流，其中任何单个数据流被定向到多个不同的主机存储器位置。 设备控制器还可以是ECP并行端口控制器，其通过并行总线与多个不同的外围设备进行接口，其中每个外围设备作为独立和独立的数据路径出现在系统中。

公开(公告)号：US5905912A

公开(公告)日：1999-05-18

申请号：US627989

申请日：1996-04-08

申请人： Franklyn H. Story ,  David R. Evoy ,  Peter Chambers ,  Lonnie Goff

发明人： Franklyn H. Story ,  David R. Evoy ,  Peter Chambers ,  Lonnie Goff

IPC分类号： G06F13/28 ,  G06F13/00

CPC分类号： G06F13/28

摘要： The present invention relates to a system and method for implementing peripheral device bus mastering via a general purpose list processor. The system is comprised of four main elements: a bus controller, a DMA controller, a list processor, and a device controller. The system operates under two modes of operation. The two modes arise from the two distinct modules: the DMA controller and the list processor. The first mode of operation is a single buffer transfer mode which is directly compatible with a distributed DMA model. Under this mode, distributed DMA registers within the DMA controller are programmed to transfer a single contiguous buffer of data. The second mode of operation is a multiple buffer transfer mode which uses linked lists of buffer transfer descriptors to program the distributed DMA registers within the DMA controller and initiates transfers independent of software.

摘要翻译： 本发明涉及一种通过通用列表处理器实现外围设备总线主控的系统和方法。 该系统由四个主要元件组成：总线控制器，DMA控制器，列表处理器和设备控制器。 该系统在两种操作模式下运行。 这两种模式来自两个不同的模块：DMA控制器和列表处理器。 第一种操作模式是与分布式DMA模型直接兼容的单缓冲传输模式。 在此模式下，DMA控制器内的分布式DMA寄存器被编程为传送一个连续的数据缓冲区。 第二种操作模式是多缓冲传输模式，它使用缓冲传输描述符的链表来对DMA控制器内的分布式DMA寄存器进行编程，并独立于软件启动传输。

公开(公告)号：US5774743A

公开(公告)日：1998-06-30

申请号：US627987

申请日：1996-04-08

申请人： Franklyn H. Story ,  David R. Evoy ,  Peter Chambers ,  Lonnie Goff

发明人： Franklyn H. Story ,  David R. Evoy ,  Peter Chambers ,  Lonnie Goff

IPC分类号： G06F13/12 ,  G06F9/00 ,  G06F13/00

CPC分类号： G06F13/124

摘要： The present invention is a system and method for implementing peripheral device bus mastering in a mobile computer system. The system uses the micro-controller of the mobile computer system to program a DMA controller. The DMA controller transfers data to and from the memory of the mobile computer system. A bus controller which is coupled to both the micro-controller and the DMA controller implements a memory data transfer request from the DMA controller and the micro-controller. A device controller, either a IDE hard disk controller or an ECP parallel port controller, is also coupled to the DMA controller and the micro-controller. The device controller receives and responds to the command signals from the micro-controller by transferring data to and from the DMA controller means and generating a completion signal when the transfer is complete.

摘要翻译： 本发明是一种用于在移动计算机系统中实现外围设备总线主控的系统和方法。 该系统使用移动计算机系统的微控制器对DMA控制器进行编程。 DMA控制器将数据传送到移动计算机系统的存储器和从存储器传送数据。 耦合到微控制器和DMA控制器的总线控制器实现来自DMA控制器和微控制器的存储器数据传送请求。 设备控制器（IDE硬盘控制器或ECP并行端口控制器）也耦合到DMA控制器和微控制器。 设备控制器通过向DMA控制器装置传送数据并从DMA控制器装置传送数据来接收并响应来自微控制器的命令信号，并在传送完成时产生完成信号。

公开(公告)号：US5845151A

公开(公告)日：1998-12-01

申请号：US627992

申请日：1996-04-08

申请人： Franklyn H. Story ,  David R. Evoy ,  Peter Chambers ,  Lonnie Goff

发明人： Franklyn H. Story ,  David R. Evoy ,  Peter Chambers ,  Lonnie Goff

IPC分类号： G06F13/28 ,  G06F13/00

CPC分类号： G06F13/28

摘要： The present invention is a desktop personal computer (PC) system having peripheral device bus mastering. The system has a Direct Memory Access (DMA) controller for transferring data to and from the memory of the desktop PC system. A hardware state machine is used for programming the DMA controller, generating and sending command signals, and receiving completion status after the transfer of data is complete. A bus controller is used for implementing a memory data transfer request from the DMA controller means and said hardware state machine means. A device controller, either a Universal Serial Bus (USB) controller or an Infrared Data Association (IrDA) controller, is used for receiving and responding to the command signals from the hardware state machine means, transferring data to and from the DMA controller means, and generating and returning a completion status to the hardware state machine means after the transfer of data is complete.

摘要翻译： 本发明是具有外围设备总线母盘的台式个人计算机（PC）系统。 该系统具有直接存储器访问（DMA）控制器，用于向台式PC系统的存储器传送数据。 硬件状态机用于对DMA控制器进行编程，生成和发送命令信号，并在数据传输完成后接收完成状态。 总线控制器用于实现来自DMA控制器装置和所述硬件状态机装置的存储器数据传送请求。 使用通用串行总线（USB）控制器或红外数据协会（IrDA）控制器的设备控制器来接收和响应来自硬件状态机装置的命令信号，向DMA控制器装置传送数据和从DMA控制器装置传送数据， 并且在数据传送完成之后产生并返回到硬件状态机装置的完成状态。

公开(公告)号：US5774744A

公开(公告)日：1998-06-30

申请号：US627986

申请日：1996-04-08

申请人： Franklyn H. Story ,  David R. Evoy ,  Peter Chambers ,  Lonnie Goff

发明人： Franklyn H. Story ,  David R. Evoy ,  Peter Chambers ,  Lonnie Goff

IPC分类号： G06F13/28 ,  G06F13/42 ,  G06F13/00

CPC分类号： G06F13/4291 ,  G06F13/28

摘要： The present invention relates to a system and method for implementing peripheral device bus mastering in a mobile computer system. The system uses the mobile computer system's microcontroller for programming a DMA controller, generating and sending command signals, and receiving completion status after transfer of data is complete. The micro-controller accesses a data buffer descriptor list. The data buffer descriptor list describes each data transfer that the micro-controller initiates, controls, and completes. The Direct Memory Access controller which is programmed by the micro-controller transfers data to and from a memory section of the mobile computer system. A bus controller is used for implementing a memory data transfer request from the DMA controller means and the micro-controller means. A device controller such as a Universal Serial Bus (USB) controller or an Infrared Data Association (IrDA) controller is used for receiving and responding to command signals from the micro-controller, transferring data to and from the DMA controller, and generating and returning a completion status to the micro-controller after the transfer of data is complete.

摘要翻译： 本发明涉及一种用于在移动计算机系统中实现外围设备总线主控的系统和方法。 该系统使用移动计算机系统的微控制器对DMA控制器进行编程，生成和发送命令信号，并在数据传输完成后接收完成状态。 微控制器访问数据缓冲区描述符列表。 数据缓冲区描述符列表描述了微控制器启动，控制和完成的每个数据传输。 由微控制器编程的直接存储器访问控制器将数据传送到移动计算机系统的存储器部分和从存储器部分传送数据。 总线控制器用于实现来自DMA控制器装置和微控制器装置的存储器数据传送请求。 使用诸如通用串行总线（USB）控制器或红外数据协会（IrDA）控制器的设备控制器来接收和响应来自微控制器的命令信号，向DMA控制器传送数据和从DMA控制器传送数据，以及生成和返回 数据传输完成后微控制器的完成状态。

公开(公告)号：US5961640A

公开(公告)日：1999-10-05

申请号：US838021

申请日：1997-04-22

申请人： Peter Chambers ,  Scott Edward Harrow ,  David Evoy

发明人： Peter Chambers ,  Scott Edward Harrow ,  David Evoy

IPC分类号： G06F7/76 ,  G06F13/40 ,  G06F17/00

CPC分类号： G06F7/768 ,  G06F13/4013

摘要： An endian domain conversion circuit for converting data packets transmitted between two bus interfaces. The novel system advantageously eliminates any requirement for a large bit switch within the circuit's write data path. Instead, endian conversion intelligence is placed into the read data path. Double words (dwords) are individually received from an incoming data packet and bytes are parallel stored into the same byte location of several different first-in-first-out (FIFO) memories. In one example, the dwords are 32-bits each and the number FIFO memories used is four. An entire input data packet is received in this manner, incrementing the write address of the FIFO memories for each dword. Depending on the type of endian domain conversion required, if at all, endian conversion control circuitry of the present invention controls the manner in which the four exemplary FIFO memories are read (via a read pointer) and the manner which their data is supplied over the output bus to generate the output data. In one embodiment, a byte stream is generated over the output bus. Alternatively, dwords are sent over the output bus in proper endian domain format. Data descriptors located in a data packet header define the endian input domain format, the expected endian output domain format, the data packet size and the start address in system memory of the input data packet. The novel system is well suited to process arbitrarily sized data packets as well as data packets starting at arbitrary byte boundaries.

摘要翻译： 一种用于转换在两个总线接口之间传输的数据分组的端序域转换电路。 该新颖系统有利地消除了对电路的写入数据路径内的大位开关的任何要求。 相反，endian转换智能被放置在读取数据路径中。 从输入数据分组单独接收双字（双字），字节并行存储到几个不同的先进先出（FIFO）存储器的相同字节位置。 在一个示例中，双字为32位，使用的FIFO存储器数为4。 以这种方式接收整个输入数据分组，增加每个双字的FIFO存储器的写入地址。 根据所需的字节序转换类型，如果根本不存在本发明的字节序转换控制电路，则控制四个典型的FIFO存储器（经由读指针）读取的方式以及它们的数据在 输出总线产生输出数据。 在一个实施例中，在输出总线上产生字节流。 或者，双字通过输出总线以适当的字符串格式发送。 位于数据包头部中的数据描述符定义输入数据包的系统存储器中的端序输入域格式，预期端输出域格式，数据包大小和起始地址。 该新颖的系统非常适合于处理任意大小的数据分组以及从任意字节边界开始的数据分组。

公开(公告)号：US20070139076A1

公开(公告)日：2007-06-21

申请号：US11676070

申请日：2007-02-16

申请人： Peter Chambers

发明人： Peter Chambers

IPC分类号： H03K19/00

CPC分类号： H03K19/1731 ,  H01L2224/49113

摘要： A circuit coupled to an input-output bond pad (I/O pad) in an integrated circuit including an input buffer, an output buffer and a pad management circuit. The pad management circuit receives a first data signal, a first output enable signal, and a configuration signal indicative of the connection state of the I/O pad, and generates a second data signal and a second output enable signal. When the configuration signal indicates the I/O pad is to be connected to a package pin, the pad management circuit couples the first data signal as the second data signal and couples the first output enable signal as the second output enable signal. When the configuration signal indicates the I/O pad is to be left unconnected, the pad management circuit asserts the second output enable signal and generates the second data signal having a predetermined value.

摘要翻译： 一种耦合到包括输入缓冲器，输出缓冲器和焊盘管理电路的集成电路中的输入 - 输出接合焊盘（I / O焊盘）的电路。 焊盘管理电路接收第一数据信号，第一输出使能信号和表示I / O焊盘的连接状态的配置信号，并产生第二数据信号和第二输出使能信号。 当配置信号指示将I / O焊盘连接到封装引脚时，焊盘管理电路将第一数据信号作为第二数据信号耦合，并将第一输出使能信号耦合作为第二输出使能信号。 当配置信号指示I / O焊盘不连接时，焊盘管理电路确定第二输出使能信号并产生具有预定值的第二数据信号。

公开(公告)号：US20050131973A1

公开(公告)日：2005-06-16

申请号：US10759988

申请日：2004-01-15

申请人： Peter Chambers ,  Joseph Judkins

发明人： Peter Chambers ,  Joseph Judkins

IPC分类号： G06F7/00

CPC分类号： H03M1/1235 ,  H03M1/129

摘要： A device for performing numerical value conversion of a digital input value in a first unit to a second, natural unit where the digital input value is a digitized value of a first measurement parameter includes a look-up table storing an array of coefficients for performing the numerical value conversion for multiple measurement parameters. The look-up table is indexed using a first parameter indicative of the first measurement parameter to provide a selected coefficient. The device further includes an arithmetic logic unit (ALU) receiving the digital input value and the selected coefficient and performing the numerical value conversion based on a first equation and the selected coefficient to compute a digital output value. The device also includes a saturation-limit circuit coupled to receive the digital output value from the arithmetic logic unit and provide a predetermined output value when the digital output value exceeds a predetermined maximum value.

摘要翻译： 一种用于对第一单元中的数字输入值进行数值转换的装置，其中数字输入值是第一测量参数的数字化值的第二自然单元包括：存储用于执行第一测量参数的系数阵列的查找表; 多个测量参数的数值转换。 使用指示第一测量参数的第一参数来索引查找表以提供所选择的系数。 该装置还包括接收数字输入值和所选系数的算术逻辑单元（ALU），并且基于第一方程和所选择的系数执行数值转换以计算数字输出值。 该装置还包括饱和极限电路，其被耦合以从所述算术逻辑单元接收所述数字输出值，并且当所述数字输出值超过预定最大值时提供预定的输出值。

公开(公告)号：US06898680B2

公开(公告)日：2005-05-24

申请号：US10336296

申请日：2003-01-03

申请人： Peter Chambers

发明人： Peter Chambers

IPC分类号： G06F12/00 ,  G06F12/12 ,  G11C16/10 ,  G11C16/34

CPC分类号： G11C16/3459 ,  G11C16/10 ,  G11C16/3454 ,  G11C16/349

摘要： A method and structure are provided that reduce the overall time of the read-erase-modify-write cycle time of non-volatile memories. Specifically, the erase operation of the read-erase-write cycle is avoided in certain circumstances. In one embodiment, the erase operation is skipped where a predetermined pattern is found in at least a portion the block. In another embodiment, the erase operation is skipped where a status of the block indicates that the erase operation can be skipped.

摘要翻译： 提供了减少非易失性存储器的读擦除修改 - 写周期时间的总时间的方法和结构。 具体地说，在某些情况下避免了擦写写周期的擦除操作。 在一个实施例中，擦除操作被跳过，其中在块的至少一部分中发现预定模式。 在另一个实施例中，跳过擦除操作，其中块的状态指示可以跳过擦除操作。