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    Method for production of charge-trapping memory devices
    1.
    发明授权
    Method for production of charge-trapping memory devices 失效
    电荷俘获存储器件的制造方法

    公开(公告)号：US07026220B1

    公开(公告)日：2006-04-11

    申请号：US11006484

    申请日：2004-12-07

    申请人： Georg Tempel ,  Elard Stein von Kamienski ,  Stephan Riedel ,  Veronika Polei ,  Roland Haberkern ,  Roman Knoefler

    发明人： Georg Tempel ,  Elard Stein von Kamienski ,  Stephan Riedel ,  Veronika Polei ,  Roland Haberkern ,  Roman Knoefler

    IPC分类号： H01L21/336 ,  H01L21/3205

    CPC分类号： H01L27/11568 ,  H01L27/115 ,  Y10S438/954

    摘要： The method aims at improving the charge confinement of the memory layer at the edges facing the regions of buried bitlines. After the deposition of the memory layer between confinement layers and the implantation of dopants for bitlines and source/drain regions, an oxidation of semiconductor material to form upper bitline isolation regions takes place. By this method, additional oxide regions are produced at the edges of the memory layer in the same oxidation step. Either a silicon layer may be deposited and reduced to sidewall spacers, which are subsequently oxidized; or recesses are etched into the memory layer and subsequently filled with semiconductor oxide.

    摘要翻译： 该方法旨在改善面向掩埋位线区域的边缘处的存储层的电荷限制。 在限制层之间的存储层沉积和用于位线和源/漏区的掺杂剂的注入之后，发生半导体材料的氧化以形成上位线隔离区。 通过该方法，在相同的氧化步骤中在存储层的边缘产生附加的氧化物区域。 可以将硅层沉积并还原成侧壁间隔物，其随后被氧化; 或凹槽蚀刻到存储层中，随后填充半导体氧化物。

    Memory cell fabrication method and memory cell configuration
    2.
    发明授权
    Memory cell fabrication method and memory cell configuration 有权
    存储单元制造方法和存储单元配置

    公开(公告)号：US06627498B2

    公开(公告)日：2003-09-30

    申请号：US10093722

    申请日：2002-03-08

    申请人： Josef Willer ,  Veronika Polei

    发明人： Josef Willer ,  Veronika Polei

    IPC分类号： H01L218247

    CPC分类号： H01L29/7923 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568

    摘要： The memory cell has a source region and a drain region in semiconductor material and, above a channel region between the source and drain regions, a three-layered layer structure with a storage layer between boundary layers and a gate electrode arranged thereon. The storage layer is replaced above the channel region by an etching layer made of Al2O3. During fabrication, the etching layer is etched out laterally and the second boundary layer is thus undercut. The resulting interspaces are filled with the material of the storage layer. The provision of suitable spacers makes it possible to define the dimensions of the memory cell.

    摘要翻译： 存储单元在半导体材料中具有源极区域和漏极区域，并且在源极和漏极区域之间的沟道区域之上，具有在边界层之间的存储层和布置在其上的栅电极的三层层结构。 通过由Al 2 O 3制成的蚀刻层在沟道区域之上替换存储层。 在制造过程中，蚀刻层被横向蚀刻，因此第二边界层被切割。 所产生的间隙填充有存储层的材料。 提供合适的间隔物使得可以限定存储单元的尺寸。

    Method for forming a semiconductor product and semiconductor product
    3.
    发明申请
    Method for forming a semiconductor product and semiconductor product 失效
    用于形成半导体产品和半导体产品的方法

    公开(公告)号：US20070001305A1

    公开(公告)日：2007-01-04

    申请号：US11172366

    申请日：2005-06-30

    申请人： Thomas Mikolajick ,  Torsten Mueller ,  Nicolas Nagel ,  Lars Bach ,  Dominik Olligs ,  Veronika Polei

    发明人： Thomas Mikolajick ,  Torsten Mueller ,  Nicolas Nagel ,  Lars Bach ,  Dominik Olligs ,  Veronika Polei

    IPC分类号： H01L23/52 ,  H01L21/4763

    CPC分类号： H01L21/76816 ,  H01L21/76838 ,  H01L27/115 ,  H01L27/11568

    摘要： A semiconductor product includes, a substrate with a first dielectric layer having contact hole fillings for contacting active areas in the substrate. A second dielectric layer with contact holes is provided therein. The contact holes have a width in a first lateral direction. The product further includes conductive lines, each conductive line passing over contact holes in the second dielectric layer and contacting a plurality of contact hole fillings in the first dielectric layer. The conductive lines have a width, in the first lateral direction, that is smaller than the width of the contact holes of the second dielectric layer. The conductive lines are in direct mechanical contact with the contact hole fillings and thereby remove the need to provide any conventional “contact to interconnect” structures.

    摘要翻译： 半导体产品包括具有第一电介质层的衬底，该第一电介质层具有用于接触衬底中的有源区的接触孔填充物。 在其中设置有具有接触孔的第二介质层。 接触孔在第一横向具有宽度。 该产品还包括导线，每个导线穿过第二介电层中的接触孔，并接触第一介电层中的多个接触孔填充物。 导电线在第一横向方向上的宽度小于第二介电层的接触孔的宽度。 导线与接触孔填充物直接机械接触，从而消除了提供任何传统的“接触互连”结构的需要。

    Method for producing an antifuse and antifuse for the selective electrical connection of adjacent conductive regions
    4.
    发明授权
    Method for producing an antifuse and antifuse for the selective electrical connection of adjacent conductive regions 失效
    用于制造用于相邻导电区域的选择性电连接的反熔丝和反熔丝的方法

    公开(公告)号：US06716678B2

    公开(公告)日：2004-04-06

    申请号：US10378243

    申请日：2003-03-03

    申请人： Matthias Lehr ,  Uwe Schilling ,  Veronika Polei ,  Irene Sperl

    发明人： Matthias Lehr ,  Uwe Schilling ,  Veronika Polei ,  Irene Sperl

    IPC分类号： H01L2182

    CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for producing antifuse structures and antifuses by which adjacent conductive regions can be selectively electrically connected involve the application of a sacrificial layer to a first conductive region. The sacrificial layer is patterned with the aid of a photolithographic method. A fuse layer is applied and the sacrificial layer is then removed. A non-conductive layer is applied and a conductive material is introduced in an opening in the non-conductive layer for the purpose of forming a second conductive region.

    摘要翻译： 用于制造反熔丝结构和反熔丝的方法，通过其可以选择性地电连接相邻导电区域，涉及将牺牲层施加到第一导电区域。 借助于光刻方法对牺牲层进行图案化。 施加熔丝层，然后去除牺牲层。 施加非导电层，并且为了形成第二导电区域，在非导电层中的开口中引入导电材料。

    Method for forming a semiconductor product and semiconductor product
    5.
    发明授权
    Method for forming a semiconductor product and semiconductor product 失效
    用于形成半导体产品和半导体产品的方法

    公开(公告)号：US07521351B2

    公开(公告)日：2009-04-21

    申请号：US11172366

    申请日：2005-06-30

    申请人： Thomas Mikolajick ,  Torsten Mueller ,  Nicolas Nagel ,  Lars Bach ,  Dominik Olligs ,  Veronika Polei

    发明人： Thomas Mikolajick ,  Torsten Mueller ,  Nicolas Nagel ,  Lars Bach ,  Dominik Olligs ,  Veronika Polei

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76816 ,  H01L21/76838 ,  H01L27/115 ,  H01L27/11568

    摘要： A semiconductor product includes, a substrate with a first dielectric layer having contact hole fillings for contacting active areas in the substrate. A second dielectric layer with contact holes is provided therein. The contact holes have a width in a first lateral direction. The product further includes conductive lines, each conductive line passing over contact holes in the second dielectric layer and contacting a plurality of contact hole fillings in the first dielectric layer. The conductive lines have a width, in the first lateral direction, that is smaller than the width of the contact holes of the second dielectric layer. The conductive lines are in direct mechanical contact with the contact hole fillings and thereby remove the need to provide any conventional “contact to interconnect” structures.

    摘要翻译： 半导体产品包括具有第一电介质层的衬底，该第一电介质层具有用于接触衬底中的有源区的接触孔填充物。 在其中设置有具有接触孔的第二介质层。 接触孔在第一横向具有宽度。 该产品还包括导线，每个导线穿过第二介电层中的接触孔，并接触第一介电层中的多个接触孔填充物。 导电线在第一横向方向上的宽度小于第二介电层的接触孔的宽度。 导线与接触孔填充物直接机械接触，从而消除了提供任何传统的“接触互连”结构的需要。

    Method for forming a semiconductor product and semiconductor product
    6.
    发明申请
    Method for forming a semiconductor product and semiconductor product 审中-公开
    用于形成半导体产品和半导体产品的方法

    公开(公告)号：US20070077748A1

    公开(公告)日：2007-04-05

    申请号：US11241877

    申请日：2005-09-30

    申请人： Dominik Olligs ,  Hocine Boubekeur ,  Veronika Polei ,  Nicolas Nagel ,  Torsten Mueller ,  Lars Bach ,  Thomas Mikolajick ,  Joachim Deppe

    发明人： Dominik Olligs ,  Hocine Boubekeur ,  Veronika Polei ,  Nicolas Nagel ,  Torsten Mueller ,  Lars Bach ,  Thomas Mikolajick ,  Joachim Deppe

    IPC分类号： H01L21/4763 ,  H01L21/3205 ,  H01L21/44

    CPC分类号： H01L27/115 ,  H01L21/76838 ,  H01L27/11521 ,  H01L27/11568

    摘要： A semiconductor product (1) includes a plurality of wordlines extending along a first lateral direction (x) along a substrate surface (22) and also includes contact structures (3) as well as filling structures (4) therebetween. Along the first direction (x) the contact structures (3) and the filling structures (4) are arranged in alternating order between two respective wordlines. Each contact structure (3) serves to connect two active areas (23) separated by one respective trench isolation filling (24) to a respective bitline (14). Accordingly, the width of the first contact structures (3) is much larger than the width of the bitlines (14) along the first direction (x). According to embodiments of the invention, tapered upper portions (9) of the contact structures (3) are shaped, the upper portions (9) having a width being significantly smaller than the width of the contact structures (3) along the first direction (x). Thereby, forming the bitlines (14) in direct contact to top surfaces (7) of contact structures (3) is possible without the risk of short circuits between adjacent bitlines (14).

    摘要翻译： 半导体产品（1）包括沿衬底表面（22）沿着第一横向（x）延伸的多个字线，并且还包括接触结构（3）以及它们之间的填充结构（4）。 沿着第一方向（x），接触结构（3）和填充结构（4）以两个相应字线之间的交替顺序排列。 每个接触结构（3）用于将由一个相应的沟槽隔离填充物（24）分开的两个有效区域（23）连接到相应的位线（14）。 因此，第一接触结构（3）的宽度比沿着第一方向（x）的位线（14）的宽度大得多。 根据本发明的实施例，接触结构（3）的锥形上部（9）成形，上部（9）的宽度明显小于接触结构（3）沿着第一方向（3）的宽度 X）。 因此，形成与接触结构（3）的顶表面（7）直接接触的位线（14）是可能的，而不会在相邻位线（14）之间发生短路。

    Method for producing bit lines for UCP flash memories
    7.
    发明授权
    Method for producing bit lines for UCP flash memories 有权
    用于产生UCP闪存的位线的方法

    公开(公告)号：US07485542B2

    公开(公告)日：2009-02-03

    申请号：US11194059

    申请日：2005-07-29

    申请人： Achim Gratz ,  Mayk Roehrich ,  Veronika Polei

    发明人： Achim Gratz ,  Mayk Roehrich ,  Veronika Polei

    IPC分类号： H01L21/76

    CPC分类号： H01L27/11521 ,  H01L27/115

    摘要： A semiconductor device can be fabricated by forming a floating gate layer over a semiconductor body. The floating gate layer is at least partially arranged over an insulation region in the semiconductor body. The floating gate layer is patterned to expose a portion of the insulation region. A recess is formed in a portion of the insulation region exposed by the patterned floating gate layer. A conductor is deposited within the recess. The conductor serves as a buried bitline. An insulator can then be formed within the recess over the conductor.

    摘要翻译： 可以通过在半导体本体上形成浮栅来制造半导体器件。 所述浮栅层至少部分地布置在所述半导体本体中的绝缘区域的上方。 将浮栅层图案化以暴露绝缘区域的一部分。 在由图案化的浮栅层露出的绝缘区域的一部分中形成凹部。 导体沉积在凹槽内。 导体作为埋地位线。 然后可以在导体的凹部内形成绝缘体。

    Method for fabricating a buried bit line for a semiconductor memory
    9.
    发明授权
    Method for fabricating a buried bit line for a semiconductor memory 失效
    一种用于半导体存储器的掩埋位线的制造方法

    公开(公告)号：US07074678B2

    公开(公告)日：2006-07-11

    申请号：US10623843

    申请日：2003-07-21

    申请人： Veronika Polei ,  Mayk Röhrich ,  Achim Gratz

    发明人： Veronika Polei ,  Mayk Röhrich ,  Achim Gratz

    IPC分类号： H01L21/336

    CPC分类号： H01L21/2257 ,  H01L21/743

    摘要： In a method for fabricating a buried bit line for a semiconductor memory, the buried bit line is produced as a diffusion region using a dopant source including polysilicon that has previously been applied above the region intended for the buried bit line. This keeps the extent of diffusion within limits and means that the doped polysilicon is particularly suitable for the formation of the insulating oxide region above the buried bit line, due to the rapid oxidation.

    摘要翻译： 在制造用于半导体存储器的掩埋位线的方法中，使用预先施加在用于掩埋位线的区域之上的包含多晶硅的掺杂源，产生掩埋位线作为扩散区域。 这将扩散范围保持在极限范围内，并且意味着掺杂多晶硅特别适用于由于快速氧化而形成掩埋位线上方的绝缘氧化物区域。