公开(公告)号：US20160141257A1

公开(公告)日：2016-05-19

申请号：US15005275

申请日：2016-01-25

Applicant: GEORGIA TECH RESEARCH CORPORATION

Inventor： Venkatesh Sundaram ,  Fuhan Liu ,  Rao R. Tummala ,  Vijay Sukumaran ,  Vivek Sridharan ,  Qiao Chen

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L23/562 ,  H01L21/486 ,  H01L21/76843 ,  H01L23/15 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2924/01019 ,  H01L2924/15311

Abstract: Disclosed herein are, for instance, methods for producing through package vias in a glass interposer. For instance, disclosed herein is a method for producing through package vias in a glass interposer comprising laminating a polymer on at least a portion of a top surface of a glass interposer, removing at least a portion of the polymer and the glass interposer to form a through via, filling at least a portion of the through via with a metal conductor to form a metallization layer, and selectively removing a portion of the metallization layer to form a metalized through package via. Other methods are also disclosed, along with through-package-via structures in glass interposers produced therefrom.

Abstract translation: 这里公开的是例如在玻璃插入件中通过封装通孔生产的方法。 例如，本文公开了一种用于在玻璃插入件中通过封装通孔生产的方法，包括在玻璃插入件的顶表面的至少一部分上层压聚合物，去除至少一部分聚合物和玻璃插入物以形成 通孔，用金属导体填充通孔的至少一部分以形成金属化层，并且选择性地去除金属化层的一部分以形成金属化的封装通孔。 还公开了其它方法，以及由其制造的玻璃中间体中的贯穿封装通孔结构。

公开(公告)号：US20160109653A1

公开(公告)日：2016-04-21

申请号：US14884242

申请日：2015-10-15

Applicant: GEORGIA TECH RESEARCH CORPORATION

Inventor： William A. Vis ,  Bruce Chia-Te Chou ,  Venkatesh Sundaram ,  Rao R. Tummala ,  Terry P. Bowen ,  Jibin Sun

IPC: G02B6/12 ,  G02B6/26 ,  G02B6/122 ,  G02B6/136 ,  G02B6/132

CPC classification number: G02B6/1221 ,  G02B6/4202 ,  G02B2006/12069

Abstract: An embodiment provides an optical interconnect comprising first and second planar metallization layers, a glass substrate disposed between at least portions of the first and second metallization layers, an aperture in the second metallization layer having a first and second ends, and a polymer waveguide having a first end adjacent the first end of the aperture. The first end of the waveguide can have a first edge defining a first acute angle with respect to a top surface of the waveguide. The first end of the optical waveguide can be configured to receive an optical signal traversing through the glass substrate from a source proximate a first position on a top surface of the glass substrate and direct the optical signal with the first edge in a direction parallel to the glass substrate towards a second end of the waveguide.

Abstract translation: 实施例提供了包括第一和第二平面金属化层的光学互连，设置在第一和第二金属化层的至少部分之间的玻璃衬底，第二金属化层中的孔具有第一和第二端，以及聚合物波导，其具有 第一端邻近孔的第一端。 波导的第一端可以具有相对于波导的顶表面限定第一锐角的第一边缘。 光波导的第一端可以被配置为接收从玻璃基板的顶表面附近的第一位置处的源极穿过玻璃基板的光信号，并且将光信号与第一边缘沿平行于玻璃基板的方向引导 玻璃基板朝向波导的第二端。

公开(公告)号：US20140355931A1

公开(公告)日：2014-12-04

申请号：US14288680

申请日：2014-05-28

Applicant: Georgia Tech Research Corporation

Inventor： Rao R. Tummala ,  Chia-Te Chou ,  Venkatesh Sundaram

IPC: G02B6/122 ,  G02B6/136

CPC classification number: G02B6/43 ,  H05K1/0274 ,  H05K2201/09827

Abstract: An optical interposer that includes a glass substrate having one or more optical vias extending through the glass substrate. A first optical polymer may be bonded to the substrate and to interior surfaces of the one or more optical vias. Implementations include one or more optical via cores comprising a second optical polymer that has a greater refractive index than the first optical polymer. The one or more optical via cores may be at least partially surrounded by the first optical polymer. Embodiments include encapsulated optical waveguides in communication with the optical vias and/or via cores. Example implementations include layers of electrical insulation, electrical traces, and electrical vias. A method of manufacture includes forming the optical vias by laser ablation. Certain embodiments may include chemically etching the inside of the vias to improve surface roughness.

Abstract translation: 一种光学插入器，其包括具有延伸穿过玻璃基板的一个或多个光学通孔的玻璃基板。 第一光学聚合物可以结合到基底和一个或多个光学通孔的内表面。 实施方案包括一个或多个光学通孔芯，其包含具有比第一光学聚合物更大的折射率的第二光学聚合物。 一个或多个光学通孔芯可以至少部分地被第一光学聚合物包围。 实施例包括与光通孔和/或通孔芯通信的封装光波导。 示例实现包括电绝缘层，电迹线和电气通孔。 一种制造方法包括通过激光烧蚀形成光学通孔。 某些实施例可以包括化学蚀刻通孔内部以改善表面粗糙度。

公开(公告)号：US12027453B2

公开(公告)日：2024-07-02

申请号：US17433801

申请日：2020-02-26

Applicant: GEORGIA TECH RESEARCH CORPORATION

Inventor： Nobuo Ogura ,  Siddharth Ravichandran ,  Venkatesh V. Sundaram ,  Rao R. Tummala

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/49822 ,  H01L21/4803 ,  H01L21/4857 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/49827 ,  H01L23/562

Abstract: The present disclosure describes semiconductor packages and, more particularly, chip-embedded semiconductor packages. The packages include core panels with apertures extending through the core panel. Semiconductor chips are embedded within chip apertures. A molding compound can be positioned along one side of the core panel. In some examples, the semiconductor chips are embedded within the molding compound. In other examples, the semiconductor chips are adhered to the molding compound. The coefficient of thermal expansion (CTE) values of the core panels described herein can be tailored to decrease warpage of the package as the semiconductor chip heats during use.

公开(公告)号：US20230215762A1

公开(公告)日：2023-07-06

申请号：US18182032

申请日：2023-03-10

Applicant: Georgia Tech Research Corporation

Inventor： Pratik Nimbalkar ,  Mohanalingam Kathaperumal ,  Madhavan Swaminathan ,  Rao R. Tummala

IPC: H01L21/768

CPC classification number: H01L21/76865 ,  H01L21/76873 ,  H01L21/76879

Abstract: Disclosed herein are methods for etch barrier deposition that can include depositing a seed layer onto a substrate, depositing a metal layer onto the seed layer in a predetermined pattern, coating the metal layer with a barrier layer, directionally etching the barrier layer from a direction orthogonal to the substrate such that at least a portion of the barrier layer oriented parallel to the direction of the directional etching remains coated on the metal layer, and etching the portion of the seed layer to remove the seed layer from the substrate.

公开(公告)号：US09417415B2

公开(公告)日：2016-08-16

申请号：US14288680

申请日：2014-05-28

Applicant: Georgia Tech Research Corporation

Inventor： Rao R. Tummala ,  Chia-Te Chou ,  Venkatesh Sundaram

IPC: G02B6/43 ,  G02B6/136 ,  H05K1/02

CPC classification number: G02B6/43 ,  H05K1/0274 ,  H05K2201/09827

Abstract: An optical interposer that includes a glass substrate having one or more optical vias extending through the glass substrate. A first optical polymer may be bonded to the substrate and to interior surfaces of the one or more optical vias. Implementations include one or more optical via cores comprising a second optical polymer that has a greater refractive index than the first optical polymer. The one or more optical via cores may be at least partially surrounded by the first optical polymer. Embodiments include encapsulated optical waveguides in communication with the optical vias and/or via cores. Example implementations include layers of electrical insulation, electrical traces, and electrical vias. A method of manufacture includes forming the optical vias by laser ablation. Certain embodiments may include chemically etching the inside of the vias to improve surface roughness.

Abstract translation: 一种光学插入器，其包括具有延伸穿过玻璃基板的一个或多个光学通孔的玻璃基板。 第一光学聚合物可以结合到基底和一个或多个光学通孔的内表面。 实施方案包括一个或多个光学通孔芯，其包含具有比第一光学聚合物更大的折射率的第二光学聚合物。 一个或多个光学通孔芯可以至少部分地被第一光学聚合物包围。 实施例包括与光通孔和/或通孔芯通信的封装光波导。 示例实现包括电绝缘层，电迹线和电气通孔。 一种制造方法包括通过激光烧蚀形成光学通孔。 某些实施例可以包括化学蚀刻通孔内部以改善表面粗糙度。

公开(公告)号：US11756985B2

公开(公告)日：2023-09-12

申请号：US16764585

申请日：2017-11-16

Applicant: Georgia Tech Research Corporation ,  NITTO DENKO CORPORATION

Inventor： Markondeya Raj Pulugurtha ,  Yoshihiro Furukawa ,  Himani Sharma ,  Keiji Takemura ,  Rao R. Tummala ,  Teng Sun

IPC: H01F27/24 ,  H01L49/02 ,  H01F27/245 ,  H01F27/32 ,  H01F27/28

CPC classification number: H01L28/10 ,  H01F27/245 ,  H01F27/324 ,  H01F27/24 ,  H01F27/2871

Abstract: An exemplary embodiment of the present invention provides a planar inductor including a substrate, a first magnetic layer, a conductive coil, and a second magnetic layer. The first magnetic layer can be disposed on at least a portion of the substrate. The conductive coil can be disposed on a first portion of the first magnetic layer. The second magnetic layer can be disposed on a second portion of the first magnetic layer and on at least a portion of the conductive coil.

公开(公告)号：US20160113108A1

公开(公告)日：2016-04-21

申请号：US14919685

申请日：2015-10-21

Applicant: GEORGIA TECH RESEARCH CORPORATION

Inventor： Venkatesh SUNDARAM ,  Sung-Jin Kim ,  Fuhan Liu ,  Srikrishna Sitaraman ,  Rao R. Tummala

IPC: H05K1/02 ,  H05K3/02 ,  H05K3/06 ,  H05K1/18 ,  H05K3/40

CPC classification number: H05K3/4697 ,  H05K1/0218 ,  H05K1/183 ,  H05K2201/10083 ,  H05K2203/0733

Abstract: A electromagnetic interference shielding device is disclosed having a first substrate one or more surfaces. One or more laminates are operatively attached to the one or more surfaces of the first substrate. A cavity is provided that is defined by the first substrate and its corresponding one or more laminates and at least one inner lateral portion. The cavity is operable to receive one or more microelectromechanical system (MEMS) components. A first conductive structure integrally formed with a trench or via array of the substrate spans a thickness defined by one or more of surfaces of the first substrate, the first conductive structure operable to shield electromagnetic interference between MEMS components assembled with the first substrate.

Abstract translation: 公开了具有第一基板一个或多个表面的电磁干扰屏蔽装置。 一个或多个层压件可操作地附接到第一基板的一个或多个表面。 提供由第一基板及其对应的一个或多个层压板和至少一个内侧部分限定的空腔。 空腔可操作以接收一个或多个微机电系统（MEMS）部件。 与衬底的沟槽或通孔阵列整体形成的第一导电结构跨越由第一衬底的一个或多个表面限定的厚度，第一导电结构可操作以屏蔽与第一衬底组装的MEMS部件之间的电磁干扰。

公开(公告)号：US20240321703A1

公开(公告)日：2024-09-26

申请号：US18678251

申请日：2024-05-30

Applicant: Georgia Tech Research Corporation

Inventor： Novuo Ogura ,  Siddharth Ravichandran ,  Venkatesh V. Sundaram ,  Rao R. Tummala

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49822 ,  H01L21/4803 ,  H01L21/4857 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/49827 ,  H01L23/562

Abstract: Semiconductor packages and, more particularly, chip-embedded semiconductor packages. The packages include core panels with apertures extending through the core panel. Semiconductor chips are embedded within chip apertures. A molding compound can be positioned along one side of the core panel. The semiconductor chips can be embedded within the molding compound. The semiconductor chips also can be adhered to the molding compound. The coefficient of thermal expansion (CTE) values of the core panels can be tailored to decrease warpage of the package as the semiconductor chip heats during use.

公开(公告)号：US10672718B2

公开(公告)日：2020-06-02

申请号：US15005275

申请日：2016-01-25

Applicant: GEORGIA TECH RESEARCH CORPORATION

Inventor： Venkatesh Sundaram ,  Fuhan Liu ,  Rao R. Tummala ,  Vijay Sukumaran ,  Vivek Sridharan ,  Qiao Chen

IPC: H01L21/48 ,  H01L23/00 ,  H01L23/15 ,  H01L23/498 ,  H01L21/768 ,  H01L23/48 ,  H01L23/31

Abstract: Disclosed herein are, for instance, methods for producing through package vias in a glass interposer. For instance, disclosed herein is a method for producing through package vias in a glass interposer comprising laminating a polymer on at least a portion of a top surface of a glass interposer, removing at least a portion of the polymer and the glass interposer to form a through via, filling at least a portion of the through via with a metal conductor to form a metallization layer, and selectively removing a portion of the metallization layer to form a metalized through package via. Other methods are also disclosed, along with through-package-via structures in glass interposers produced therefrom.