公开(公告)号：US20130086581A1

公开(公告)日：2013-04-04

申请号：US13251879

申请日：2011-10-03

申请人： Giles R. Frazier ,  Michael K. Gschwind ,  Naresh Nayar

发明人： Giles R. Frazier ,  Michael K. Gschwind ,  Naresh Nayar

IPC分类号： G06F9/455

CPC分类号： G06F9/45533 ,  G06F9/45558 ,  G06F9/462 ,  G06F9/5077 ,  G06F2009/45579

摘要： Multiple machine state registers are included in a processor core to permit distinction between use of hardware facilities by applications, supervisory threads and the hypervisor. All facilities are initially disabled by the hypervisor when a partition is initialized. When any access is made to a disabled facility, the hypervisor receives an indication of which facility was accessed and sets a corresponding hardware flag in the hypervisor's machine state register. When an application attempts to access a disabled facility, the supervisor managing the operating system image receives an indication of which facility was accessed and sets a corresponding hardware flag in the supervisor's machine state register. The multiple register implementation permits the supervisor to determine whether particular hardware facilities need to have their state saved when an application context swap occurs and the hypervisor can determine which hardware facilities need to have their state saved when a partition swap occurs.

摘要翻译： 多个机器状态寄存器被包括在处理器核心中，以便区分应用程序，监督线程和管理程序之间的硬件设施的使用。 当初始化分区时，所有的设备最初被管理程序禁用。 当对残疾设施进行访问时，管理程序将收到访问哪个设施的指示，并在管理程序的机器状态寄存器中设置相应的硬件标志。 当应用程序尝试访问禁用的设备时，管理操作系统映像的主管接收到哪个设备被访问的指示，并在主管机器状态寄存器中设置相应的硬件标志。 多寄存器实现允许主管当发生应用程序上下文交换时确定特定硬件设施是否需要保存其状态，并且管理程序可以确定在发生分区交换时哪些硬件设施需要保存其状态。

公开(公告)号：US08695010B2

公开(公告)日：2014-04-08

申请号：US13251879

申请日：2011-10-03

申请人： Giles R. Frazier ,  Michael K. Gschwind ,  Naresh Nayar

发明人： Giles R. Frazier ,  Michael K. Gschwind ,  Naresh Nayar

IPC分类号： G06F9/46

CPC分类号： G06F9/45533 ,  G06F9/45558 ,  G06F9/462 ,  G06F9/5077 ,  G06F2009/45579

摘要： Multiple machine state registers are included in a processor core to permit distinction between use of hardware facilities by applications, supervisory threads and the hypervisor. All facilities are initially disabled by the hypervisor when a partition is initialized. When any access is made to a disabled facility, the hypervisor receives an indication of which facility was accessed and sets a corresponding hardware flag in the hypervisor's machine state register. When an application attempts to access a disabled facility, the supervisor managing the operating system image receives an indication of which facility was accessed and sets a corresponding hardware flag in the supervisor's machine state register. The multiple register implementation permits the supervisor to determine whether particular hardware facilities need to have their state saved when an application context swap occurs and the hypervisor can determine which hardware facilities need to have their state saved when a partition swap occurs.

摘要翻译： 多个机器状态寄存器被包括在处理器核心中，以便区分应用程序，监督线程和管理程序之间的硬件设施的使用。 当初始化分区时，所有的设备最初被管理程序禁用。 当对残疾设施进行访问时，管理程序将收到访问哪个设施的指示，并在管理程序的机器状态寄存器中设置相应的硬件标志。 当应用程序尝试访问禁用的设备时，管理操作系统映像的主管接收到哪个设备被访问的指示，并在主管机器状态寄存器中设置相应的硬件标志。 多寄存器实现允许主管当发生应用程序上下文交换时确定特定硬件设施是否需要保存其状态，并且管理程序可以确定在发生分区交换时哪些硬件设施需要保存其状态。

公开(公告)号：US20080168258A1

公开(公告)日：2008-07-10

申请号：US11621393

申请日：2007-01-09

申请人： William J. Armstrong ,  Richard L. Arndt ,  Michael J. Corrigan ,  Giles R. Frazier ,  Timothy R. Marchini ,  Cathy May ,  Naresh Nayar ,  John T. O'Quin

发明人： William J. Armstrong ,  Richard L. Arndt ,  Michael J. Corrigan ,  Giles R. Frazier ,  Timothy R. Marchini ,  Cathy May ,  Naresh Nayar ,  John T. O'Quin

IPC分类号： G06F15/76 ,  G06F9/30

CPC分类号： G06F9/30101 ,  G06F9/30181 ,  G06F9/468

摘要： A method and system for selecting the architecture level to which a processor appears to conform within a computing environment when executing specific logical partitions or programs and performing migration among different levels of processor architecture. The method utilizes a “processor compatibility register” (PCR) that controls the level of the architecture that the processor appears to support. In one embodiment, the PCR is accessible only to super-privileged software. The super-privileged software sets bits in the PCR that specify the architecture level that the processor is to appear to support so that when the program runs on the processor, the processor behaves in accordance with the architecture level for which the program was designed.

摘要翻译： 一种用于在执行特定逻辑分区或程序并且在不同级别的处理器架构之间执行迁移时，选择处理器在计算环境内符合的架构级别的方法和系统。 该方法利用“处理器兼容性寄存器”（PCR）来控制处理器似乎支持的架构级别。 在一个实施方案中，PCR仅可用于超特权软件。 超级特权软件设置PCR中的位，指定处理器将要支持的架构级别，以便当程序在处理器上运行时，处理器的行为与程序设计的架构级别相符。

公开(公告)号：US20130179886A1

公开(公告)日：2013-07-11

申请号：US13452745

申请日：2012-04-20

申请人： Giles R. Frazier ,  Bruce Mealy ,  Naresh Nayar

发明人： Giles R. Frazier ,  Bruce Mealy ,  Naresh Nayar

IPC分类号： G06F9/46

CPC分类号： G06F21/6218 ,  G06F9/3012 ,  G06F9/3851 ,  G06F9/45541 ,  G06F9/45558 ,  G06F2009/45587

摘要： Techniques for simulating exclusive use of a processor core amongst multiple logical partitions (LPARs) include providing hardware thread-dependent status information in response to access requests by the LPARs that is reflective of exclusive use of the processor by the LPAR accessing the hardware thread-dependent information. The information returned in response to the access requests is transformed if the requestor is a program executing at a privilege level lower than the hypervisor privilege level, so that each logical partition views the processor as though it has exclusive use of the processor. The techniques may be implemented by a logical circuit block within the processor core that transforms the hardware thread-specific information to a logical representation of the hardware thread-specific information or the transformation may be performed by program instructions of an interrupt handler that traps access to the physical register containing the information.

摘要翻译： 用于模拟在多个逻辑分区（LPAR）中独占使用处理器核心的技术包括提供响应于LPAR的访问请求的硬件线程依赖状态信息，所述LPAR反映了LPAR访问硬件线程相关的独占使用处理器 信息。 如果请求者是在低于管理程序权限级别的特权级别下执行的程序，则转换响应于访问请求而返回的信息，使得每个逻辑分区将处理器视为处理器的独占使用。 这些技术可以由处理器核心内的逻辑电路块来实现，其将硬件线程特定信息转换为硬件线程特定信息的逻辑表示，或者可以通过将访问陷阱的中断处理程序的程序指令执行 物理寄存器包含信息。

公开(公告)号：US09069598B2

公开(公告)日：2015-06-30

申请号：US13345002

申请日：2012-01-06

申请人： Giles R. Frazier ,  Bruce Mealy ,  Naresh Nayar

发明人： Giles R. Frazier ,  Bruce Mealy ,  Naresh Nayar

IPC分类号： G06F9/455 ,  G06F9/38

CPC分类号： G06F21/6218 ,  G06F9/3012 ,  G06F9/3851 ,  G06F9/45541 ,  G06F9/45558 ,  G06F2009/45587

摘要： Techniques for simulating exclusive use of a processor core amongst multiple logical partitions (LPARs) include providing hardware thread-dependent status information in response to access requests by the LPARs that is reflective of exclusive use of the processor by the LPAR accessing the hardware thread-dependent information. The information returned in response to the access requests is transformed if the requestor is a program executing at a privilege level lower than the hypervisor privilege level, so that each logical partition views the processor as though it has exclusive use of the processor. The techniques may be implemented by a logical circuit block within the processor core that transforms the hardware thread-specific information to a logical representation of the hardware thread-specific information or the transformation may be performed by program instructions of an interrupt handler that traps access to the physical register containing the information.

摘要翻译： 用于模拟在多个逻辑分区（LPAR）中独占使用处理器核心的技术包括提供响应于LPAR的访问请求的硬件线程依赖状态信息，所述LPAR反映了LPAR访问硬件线程相关的独占使用处理器 信息。 如果请求者是在低于管理程序权限级别的特权级别下执行的程序，则转换响应于访问请求而返回的信息，使得每个逻辑分区将处理器视为处理器的独占使用。 这些技术可以由处理器核心内的逻辑电路块来实现，其将硬件线程特定信息转换为硬件线程特定信息的逻辑表示，或者可以通过将访问陷阱的中断处理程序的程序指令执行 物理寄存器包含信息。

公开(公告)号：US08990816B2

公开(公告)日：2015-03-24

申请号：US13452745

申请日：2012-04-20

申请人： Giles R. Frazier ,  Bruce Mealy ,  Naresh Nayar

发明人： Giles R. Frazier ,  Bruce Mealy ,  Naresh Nayar

IPC分类号： G06F9/52 ,  G06F9/455 ,  G06F9/38

CPC分类号： G06F21/6218 ,  G06F9/3012 ,  G06F9/3851 ,  G06F9/45541 ,  G06F9/45558 ,  G06F2009/45587

摘要： Techniques for simulating exclusive use of a processor core amongst multiple logical partitions (LPARs) include providing hardware thread-dependent status information in response to access requests by the LPARs that is reflective of exclusive use of the processor by the LPAR accessing the hardware thread-dependent information. The information returned in response to the access requests is transformed if the requestor is a program executing at a privilege level lower than the hypervisor privilege level, so that each logical partition views the processor as though it has exclusive use of the processor. The techniques may be implemented by a logical circuit block within the processor core that transforms the hardware thread-specific information to a logical representation of the hardware thread-specific information or the transformation may be performed by program instructions of an interrupt handler that traps access to the physical register containing the information.

公开(公告)号：US07802252B2

公开(公告)日：2010-09-21

申请号：US11621393

申请日：2007-01-09

申请人： William J. Armstrong ,  Richard L. Arndt ,  Michael J. Corrigan ,  Giles R. Frazier ,  Timothy R. Marchini ,  Cathy May ,  Naresh Nayar ,  John T. O'Quin, II

发明人： William J. Armstrong ,  Richard L. Arndt ,  Michael J. Corrigan ,  Giles R. Frazier ,  Timothy R. Marchini ,  Cathy May ,  Naresh Nayar ,  John T. O'Quin, II

IPC分类号： G06F9/46 ,  G06F9/50

CPC分类号： G06F9/30101 ,  G06F9/30181 ,  G06F9/468

摘要： A method and system for selecting the architecture level to which a processor appears to conform within a computing environment when executing specific logical partitions or programs and performing migration among different levels of processor architecture. The method utilizes a “processor compatibility register” (PCR) that controls the level of the architecture that the processor appears to support. In one embodiment, the PCR is accessible only to super-privileged software. The super-privileged software sets bits in the PCR that specify the architecture level that the processor is to appear to support so that when the program runs on the processor, the processor behaves in accordance with the architecture level for which the program was designed.

摘要翻译： 一种用于在执行特定逻辑分区或程序并且在不同级别的处理器架构之间执行迁移时，选择处理器在计算环境内符合的架构级别的方法和系统。 该方法利用“处理器兼容性寄存器”（PCR）来控制处理器似乎支持的架构级别。 在一个实施方案中，PCR仅可用于超特权软件。 超级特权软件设置PCR中的位，指定处理器将要支持的架构级别，以便当程序在处理器上运行时，处理器的行为与程序设计的架构级别相符。

公开(公告)号：US20130179892A1

公开(公告)日：2013-07-11

申请号：US13345002

申请日：2012-01-06

申请人： Giles R. Frazier ,  Bruce Mealy ,  Naresh Nayar

发明人： Giles R. Frazier ,  Bruce Mealy ,  Naresh Nayar

IPC分类号： G06F9/46 ,  G06F13/24

CPC分类号： G06F21/6218 ,  G06F9/3012 ,  G06F9/3851 ,  G06F9/45541 ,  G06F9/45558 ,  G06F2009/45587

摘要： Techniques for simulating exclusive use of a processor core amongst multiple logical partitions (LPARs) include providing hardware thread-dependent status information in response to access requests by the LPARs that is reflective of exclusive use of the processor by the LPAR accessing the hardware thread-dependent information. The information returned in response to the access requests is transformed if the requestor is a program executing at a privilege level lower than the hypervisor privilege level, so that each logical partition views the processor as though it has exclusive use of the processor. The techniques may be implemented by a logical circuit block within the processor core that transforms the hardware thread-specific information to a logical representation of the hardware thread-specific information or the transformation may be performed by program instructions of an interrupt handler that traps access to the physical register containing the information.

公开(公告)号：US08645974B2

公开(公告)日：2014-02-04

申请号：US12111020

申请日：2008-04-28

申请人： William J. Armstrong ,  Charles S. Graham ,  Sandy K. Kao ,  Kyle A. Lucke ,  Naresh Nayar ,  Michal Ostrowski ,  Renato J. Recio ,  Randal C. Swanberg

发明人： William J. Armstrong ,  Charles S. Graham ,  Sandy K. Kao ,  Kyle A. Lucke ,  Naresh Nayar ,  Michal Ostrowski ,  Renato J. Recio ,  Randal C. Swanberg

IPC分类号： G06F3/00 ,  G06F9/44 ,  G06F9/46 ,  G06F13/00 ,  G06F9/455

CPC分类号： G06F12/1475 ,  G06F9/45558 ,  G06F12/1491 ,  G06F2009/45579 ,  G06F2212/1056

摘要： Multiple logical partitions are provided access to a self-virtualizing input/output device of a data processing system via multiple dedicated partition adjunct instances. Access is established by: interfacing each logical partition to one or more associated partition adjunct instances, each partition adjunct instance coupling its associated logical partition to one of a virtual function or a queue pair of the self-virtualizing input/output device, and each partition adjunct instance being a separate dispatchable state and being created employing virtual address space donated from the respective logical partition or a hypervisor of the data processing system, and each partition adjunct instance including a device driver for the virtual function or queue pair of the self-virtualizing input/output device; and providing each logical partition with at least one virtual input/output which is interfaced through the logical partition's respective partition adjunct instance(s) to a virtual function or queue pair of the self-virtualizing input/output device.

摘要翻译： 提供了多个逻辑分区，通过多个专用分区附件实例访问数据处理系统的自身虚拟化输入/输出设备。 访问是通过以下方式建立的：将每个逻辑分区连接到一个或多个相关联的分区附件实例，每个分区附件实例将其相关联的逻辑分区耦合到自虚拟输入/输出设备的虚拟功能或队列对之一，以及每个分区 辅助实例是单独的可分派状态，并且被使用从相应的逻辑分区或数据处理系统的管理程序捐赠的虚拟地址空间被创建，并且每个分区附件实例包括用于虚拟功能的虚拟功能或队列对的自身虚拟化 输入/输出设备; 以及向每个逻辑分区提供至少一个虚拟输入/输出，所述至少一个虚拟输入/输出通过所述逻辑分区的相应分区附件实例与所述自虚拟化输入/输出设备的虚拟功能或队列对连接。

公开(公告)号：US08595721B2

公开(公告)日：2013-11-26

申请号：US12644749

申请日：2009-12-22

申请人： Naresh Nayar ,  Karthick Rajamani ,  Freeman L. Rawson, III ,  Malcolm S. Ware

发明人： Naresh Nayar ,  Karthick Rajamani ,  Freeman L. Rawson, III ,  Malcolm S. Ware

IPC分类号： G06F9/455 ,  G06F9/46

CPC分类号： G06F9/45533 ,  G06F1/324 ,  G06F9/5077 ,  G06F9/5094 ,  G06F2209/5011 ,  Y02D10/126 ,  Y02D10/22 ,  Y02D10/26 ,  Y02D10/28 ,  Y02D10/36

摘要： A mechanism is provided for temporarily allocating dedicated processors to a shared processor pool. A virtual machine monitor determines whether a temporary allocation associated with an identified dedicated processor is long-term or short-term. Responsive to the temporary allocation being long-term, the virtual machine monitor determines whether an operating frequency of the identified dedicated processor is within a predetermined threshold of an operating frequency of one or more operating systems utilizing the shared processor pool. Responsive to the operating frequency of the identified dedicated processor failing to be within the predetermined threshold, the virtual machine monitor either increases or decreases the frequency of the identified dedicated processor to be within the predetermined threshold of the operating frequency of the one or more operating systems utilizing the shared processor pool and temporarily allocates the identified dedicated processor to the shared processor pool.

摘要翻译： 提供了一种用于将专用处理器临时分配给共享处理器池的机制。 虚拟机监视器确定与所识别的专用处理器相关联的临时分配是长期的还是短期的。 响应于长期的临时分配，虚拟机监视器确定所识别的专用处理器的工作频率是否在利用共享处理器池的一个或多个操作系统的操作频率的预定阈值内。 响应于所识别的专用处理器的操作频率不能在预定阈值内，虚拟机监视器将所识别的专用处理器的频率增加或降低到一个或多个操作系统的操作频率的预定阈值内 利用共享处理器池并临时将识别的专用处理器分配给共享处理器池。