公开(公告)号：US20050014349A1

公开(公告)日：2005-01-20

申请号：US10735695

申请日：2003-12-16

申请人： Glen Carey ,  Ian Jenks ,  Alan Lewis ,  Rene Lujan ,  Hailong Zhou

发明人： Glen Carey ,  Ian Jenks ,  Alan Lewis ,  Rene Lujan ,  Hailong Zhou

IPC分类号： C30B1/00 ,  H01L21/00 ,  H01L21/20 ,  H01L21/36 ,  H01L33/00 ,  H01S5/02 ,  H01S5/183 ,  H01S5/323

CPC分类号： H01S5/18305 ,  H01L21/02395 ,  H01L21/02543 ,  H01L21/02546 ,  H01L33/0079 ,  H01S5/0217 ,  H01S5/0224 ,  H01S5/141 ,  H01S5/323

摘要： A method of fabricating a semiconductor device is described. In this method, a starting substrate of sufficient thickness is selected that has the required defect density levels, which may result in an undesirable doping level. Then a semiconductor layer having a desired doping level is formed on the starting substrate. The resulting semiconductor layer has the required defect density and doping levels for the final product application. After active components, electrical conductors, and any other needed structures are formed on the semiconductor layer, the starting substrate is removed leaving a desired thickness of the semiconductor layer. In a VECSEL application, the active components can be a gain cavity, where the semiconductor layer has the necessary defect density and doping levels to maximize wall plug efficiency (WPE). In one embodiment, the doping of the semiconductor layer is not uniform. For example, a majority of the layer is doped at a low level and the remainder is doped at a much higher level. This can result in improved WPE at particular thicknesses for the higher doped material.

摘要翻译： 描述制造半导体器件的方法。 在该方法中，选择具有所需缺陷密度水平的足够厚度的起始衬底，这可能导致不期望的掺杂水平。 然后在起始衬底上形成具有期望的掺杂水平的半导体层。 所得到的半导体层具有所需的缺陷密度和最终产品应用的掺杂水平。 在有源部件之后，在半导体层上形成电导体和任何其它需要的结构，去除起始衬底，留出半导体层的所需厚度。 在VECSEL应用中，有源部件可以是增益腔，其中半导体层具有必要的缺陷密度和掺杂水平以最大化壁插拔效率（WPE）。 在一个实施例中，半导体层的掺杂不均匀。 例如，该层的大部分以低电平掺杂，其余部分以更高的水平掺杂。 这可以导致用于较高掺杂材料的特定厚度的改进的WPE。

公开(公告)号：US07973311B2

公开(公告)日：2011-07-05

申请号：US12130261

申请日：2008-05-30

申请人： Rene Lujan ,  William S. Wong

发明人： Rene Lujan ,  William S. Wong

IPC分类号： H01L31/0376 ,  H01L31/18

CPC分类号： H01L27/14658 ,  H01L27/14692

摘要： A photosensor structure includes a pixel metal layer disposed in physical and electrical contact with a pixel thin film transistor and a lower sensor layer of a p-i-n photosensor. The pixel metal layer extends laterally to an extent less that the lower sensor layer such that an overhang region is defined below the lower sensor layer and the adjacent the lateral edge of the pixel metal layer. When the relatively thick intrinsic sensor layer is formed over the lower sensor layer, it attaches to the upper surface and, due to the presence of the overhang region, the lateral edge of the lower sensor layer, forming a discrete intrinsic sensor layer structure over the pixel which is physically isolated from adjacent corresponding structures. This isolation allows for thermal expansion and contraction during formation of the intrinsic sensor layer without cracking the intrinsic sensor layer structure.

摘要翻译： 光传感器结构包括与像素薄膜晶体管物理和电接触设置的像素金属层和p-i-n光电传感器的下传感器层。 像素金属层横向延伸到较小传感器层的程度，使得悬垂区域被限定在下传感器层下方和邻近像素金属层的侧边缘。 当相对较厚的本征传感器层形成在下传感器层上时，它附着在上表面上，并且由于悬伸区域的存在，下传感器层的侧边缘形成了离散的本征传感器层结构 与相邻的相应结构物理隔离的像素。 这种隔离允许在形成本征传感器层期间的热膨胀和收缩而不破坏本征传感器层结构。

公开(公告)号：US20090294767A1

公开(公告)日：2009-12-03

申请号：US12130261

申请日：2008-05-30

申请人： Rene Lujan ,  William S. Wong

发明人： Rene Lujan ,  William S. Wong

IPC分类号： H01L31/0376 ,  H01L31/18

CPC分类号： H01L27/14658 ,  H01L27/14692

摘要： A photosensor structure includes a pixel metal layer disposed in physical and electrical contact with a pixel thin film transistor and a lower sensor layer of a p-i-n photosensor. The pixel metal layer extends laterally to an extent less that the lower sensor layer such that an overhang region is defined below the lower sensor layer and the adjacent the lateral edge of the pixel metal layer. When the relatively thick intrinsic sensor layer is formed over the lower sensor layer, it attaches to the upper surface and, due to the presence of the overhang region, the lateral edge of the lower sensor layer, forming a discrete intrinsic sensor layer structure over the pixel which is physically isolated from adjacent corresponding structures. This isolation allows for thermal expansion and contraction during formation of the intrinsic sensor layer without cracking the intrinsic sensor layer structure.

摘要翻译： 光传感器结构包括与像素薄膜晶体管物理和电接触设置的像素金属层和p-i-n光电传感器的下传感器层。 像素金属层横向延伸到较小传感器层的程度，使得悬垂区域被限定在下传感器层下方和邻近像素金属层的侧边缘。 当相对较厚的本征传感器层形成在下传感器层上时，它附着在上表面上，并且由于悬伸区域的存在，下传感器层的侧边缘形成了离散的本征传感器层结构 与相邻的相应结构物理隔离的像素。 这种隔离允许在形成本征传感器层期间的热膨胀和收缩而不破坏本征传感器层结构。

公开(公告)号：US08465795B2

公开(公告)日：2013-06-18

申请号：US12123732

申请日：2008-05-20

申请人： Rene Lujan ,  William S. Wong ,  Julia Rosolovsky Greer

发明人： Rene Lujan ,  William S. Wong ,  Julia Rosolovsky Greer

IPC分类号： B05D5/12 ,  B05D3/02

CPC分类号： H01L27/1218

摘要： A method of forming a thin-film layered electronic device over a flexible substrate comprises the steps of depositing a buffer layer over the flexible substrate, heating the substrate and buffer layer stack to a temperature at which plastic deformation of the buffer layer takes place, cooling the stack, then forming the thin-film electronic device over the plastically deformed buffer layer without further plastic deformation of the buffer layer. The heating and cooling to cause plastic deformation of the buffer layer is referred to as annealing. The thin-film electronic device is formed by a process according to which all steps are performed at a temperature below that at which further plastic deformation of the buffer layer occurs. In-process strain and runout are reduced, improving device yield on flexible substrates. An optional metal base layer may be formed over the buffer layer prior annealing.

摘要翻译： 在柔性基板上形成薄膜层状电子器件的方法包括以下步骤：在柔性衬底上沉积缓冲层，将衬底和缓冲层堆叠加热至缓冲层发生塑性变形的温度，冷却 堆叠，然后在塑性变形的缓冲层上形成薄膜电子器件，而不会使缓冲层进一步塑性变形。 将缓冲层引起塑性变形的加热和冷却称为退火。 薄膜电子器件通过一种方法形成，根据该方法，所有步骤在低于缓冲层进一步塑性变形的温度下进行。 过程中的应变和跳动减少，提高柔性基板上的器件产量。 可以在退火之前在缓冲层上形成任选的金属基层。

公开(公告)号：US07884361B2

公开(公告)日：2011-02-08

申请号：US12817127

申请日：2010-06-16

申请人： William Wong ,  Rene Lujan ,  Eugene Chow

发明人： William Wong ,  Rene Lujan ,  Eugene Chow

IPC分类号： H01L21/00

CPC分类号： H01L29/41733 ,  H01L27/124 ,  H01L27/1285 ,  H01L27/1288 ,  H01L27/1292 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66757

摘要： A self-aligned, thin-film, top-gate transistor and method of manufacturing same are disclosed. A first print-patterned mask is formed over a metal layer by digital lithography, for example by printing with a phase change material using a droplet ejector. The metal layer is then etched using the first print-patterned mask to form source and drain electrodes. A semiconductive layer and an insulative layer are formed thereover. A layer of photosensitive material is then deposited and exposed through the substrate, with the source and drain electrodes acting as masks for the exposure. Following development of the photosensitive material, a gate metal layer is deposited. A second print-patterned mask is then formed over the device, again by digital lithography. Etching and removal of the photosensitive material leaves the self-aligned top-gate electrode.

摘要翻译： 公开了一种自对准薄膜顶栅晶体管及其制造方法。 通过数字光刻在金属层上形成第一印刷图案掩模，例如通过使用液滴喷射器用相变材料进行印刷。 然后使用第一印刷图案化掩模蚀刻金属层以形成源极和漏极。 在其上形成半导体层和绝缘层。 然后将一层感光材料沉积并暴露通过基底，源极和漏极用作曝光的掩模。 在感光材料的显影之后，沉积栅极金属层。 然后再次通过数字光刻法在器件上形成第二印刷图案掩模。 蚀刻和去除感光材料离开自对准顶栅电极。

公开(公告)号：US07648860B2

公开(公告)日：2010-01-19

申请号：US12403309

申请日：2009-03-12

申请人： Rene Lujan ,  William S. Wong

发明人： Rene Lujan ,  William S. Wong

IPC分类号： H01L21/335 ,  H01L21/336

CPC分类号： H01L29/42384 ,  H01L29/4908 ,  H01L29/66757

摘要： A method of manufacturing a thin-film transistor or like structure provides conductive “tails” below an overhang region formed by a top gate structure. The tails increase in thickness as they extend outward from a point under the overhang to the source and drain contacts. The tails provide a low resistance conduction path between the source and drain regions and the channel, with low parasitic capacitance. The thickness profile of the tails is controlled by the deposition of material over and on the lateral side surfaces of the gate structure.

公开(公告)号：US20090294768A1

公开(公告)日：2009-12-03

申请号：US12130347

申请日：2008-05-30

申请人： Rene Lujan ,  William S. Wong

发明人： Rene Lujan ,  William S. Wong

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/42384 ,  H01L29/4908 ,  H01L29/66757

摘要： A method of manufacturing a thin-film transistor or like structure provides conductive “tails” below an overhang region formed by a top gate structure. The tails increase in thickness as they extend outward from a point under the overhang to the source and drain contacts. The tails provide a low resistance conduction path between the source and drain regions and the channel, with low parasitic capacitance. The thickness profile of the tails is controlled by the deposition of material over and on the lateral side surfaces of the gate structure.

公开(公告)号：US20070026585A1

公开(公告)日：2007-02-01

申请号：US11193847

申请日：2005-07-28

申请人： William Wong ,  Rene Lujan ,  Eugene Chow

发明人： William Wong ,  Rene Lujan ,  Eugene Chow

IPC分类号： H01L21/84

CPC分类号： H01L29/41733 ,  H01L27/124 ,  H01L27/1285 ,  H01L27/1288 ,  H01L27/1292 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66757

摘要： A self-aligned, thin-film, top-gate transistor and method of manufacturing same are disclosed. A first print-patterned mask is formed over a metal layer by digital lithography, for example by printing with a phase change material using a droplet ejector. The metal layer is then etched using the first print-patterned mask to form source and drain electrodes. A semiconductive layer and an insulative layer are formed thereover. A layer of photosensitive material is then deposited and exposed through the substrate, with the source and drain electrodes acting as masks for the exposure. Following development of the photosensitive material, a gate metal layer is deposited. A second print-patterned mask is then formed over the device, again by digital lithography. Etching and removal of the photosensitive material leaves the self-aligned top-gate electrode.

摘要翻译： 公开了一种自对准薄膜顶栅晶体管及其制造方法。 通过数字光刻在金属层上形成第一印刷图案掩模，例如通过使用液滴喷射器用相变材料进行印刷。 然后使用第一印刷图案化掩模蚀刻金属层以形成源极和漏极。 在其上形成半导体层和绝缘层。 然后将一层感光材料沉积并暴露通过基底，源极和漏极用作曝光的掩模。 在感光材料的显影之后，沉积栅极金属层。 然后再次通过数字光刻法在器件上形成第二印刷图案掩模。 蚀刻和去除感光材料离开自对准顶栅电极。

公开(公告)号：US07804090B2

公开(公告)日：2010-09-28

申请号：US12018794

申请日：2008-01-23

申请人： William Wong ,  Rene Lujan ,  Eugene Chow

发明人： William Wong ,  Rene Lujan ,  Eugene Chow

IPC分类号： H01L29/04

CPC分类号： H01L29/41733 ,  H01L27/124 ,  H01L27/1285 ,  H01L27/1288 ,  H01L27/1292 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66757

摘要： A self-aligned, thin-film, top-gate transistor and method of manufacturing same are disclosed. A first print-patterned mask is formed over a metal layer by digital lithography, for example by printing with a phase change material using a droplet ejector. The metal layer is then etched using the first print-patterned mask to form source and drain electrodes. A semiconductive layer and an insulative layer are formed thereover. A layer of photosensitive material is then deposited and exposed through the substrate, with the source and drain electrodes acting as masks for the exposure. Following development of the photosensitive material, a gate metal layer is deposited. A second print-patterned mask is then formed over the device, again by digital lithography. Etching and removal of the photosensitive material leaves the self-aligned top-gate electrode.

摘要翻译： 公开了一种自对准薄膜顶栅晶体管及其制造方法。 通过数字光刻在金属层上形成第一印刷图案掩模，例如通过使用液滴喷射器用相变材料进行印刷。 然后使用第一印刷图案化掩模蚀刻金属层以形成源极和漏极。 在其上形成半导体层和绝缘层。 然后将一层感光材料沉积并暴露通过基底，源极和漏极用作曝光的掩模。 在感光材料的显影之后，沉积栅极金属层。 然后再次通过数字光刻法在器件上形成第二印刷图案掩模。 蚀刻和去除感光材料离开自对准顶栅电极。

公开(公告)号：US20090289333A1

公开(公告)日：2009-11-26

申请号：US12123732

申请日：2008-05-20

申请人： Rene Lujan ,  William S. Wong ,  Julia R. Greer

发明人： Rene Lujan ,  William S. Wong ,  Julia R. Greer

IPC分类号： H01L23/58 ,  H01L21/469

CPC分类号： H01L27/1218

摘要： A method of forming a thin-film layered electronic device over a flexible substrate comprises the steps of depositing a buffer layer over the flexible substrate, heating the substrate and buffer layer stack to a temperature at which plastic deformation of the buffer layer takes place, cooling the stack, then forming the thin-film electronic device over the plastically deformed buffer layer without further plastic deformation of the buffer layer. The heating and cooling to cause plastic deformation of the buffer layer is referred to as annealing. The thin-film electronic device is formed by a process according to which all steps are performed at a temperature below that at which further plastic deformation of the buffer layer occurs. In-process strain and runout are reduced, improving device yield on flexible substrates. An optional metal base layer may be formed over the buffer layer prior annealing.

摘要翻译： 在柔性基板上形成薄膜层状电子器件的方法包括以下步骤：在柔性衬底上沉积缓冲层，将衬底和缓冲层堆叠加热至缓冲层发生塑性变形的温度，冷却 堆叠，然后在塑性变形的缓冲层上形成薄膜电子器件，而不会使缓冲层进一步塑性变形。 将缓冲层引起塑性变形的加热和冷却称为退火。 薄膜电子器件通过一种方法形成，根据该方法，所有步骤在低于缓冲层进一步塑性变形的温度下进行。 过程中的应变和跳动减少，提高柔性基板上的器件产量。 可以在退火之前在缓冲层上形成任选的金属基层。