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    Programmable interconnect point having reduced crowbar current
    1.
    发明授权
    Programmable interconnect point having reduced crowbar current 失效
    可编程互连点具有减少的撬棒电流

    公开(公告)号：US5898320A

    公开(公告)日：1999-04-27

    申请号：US823270

    申请日：1997-03-27

    申请人： Richard C. Li ,  Hy V. Nguyen ,  Patrick J. Crotty

    发明人： Richard C. Li ,  Hy V. Nguyen ,  Patrick J. Crotty

    IPC分类号： H03K19/017

    CPC分类号： H03K19/018585 ,  H03K19/00361

    摘要： Problems associated with excessive crowbar current due to input signal transitions at a buffered programmable interconnect point are solved by inserting a transistor switch between power and ground. The inserted switch is in series with the input buffer and is controlled by a memory cell which also controls the pass/no-pass state of the interconnect. An OFF inserted switch blocks current that flows during switching when the memory cell output causes a no-pass state of the interconnect.

    摘要翻译： 通过在电源和地之间插入晶体管开关来解决由于缓冲的可编程互连点处的输入信号转换引起的与过量的短路电流相关的问题。 插入的开关与输入缓冲器串联并由也控制互连的通过/不通过状态的存储器单元控制。 断开插入开关在存储单元输出导致互连的无通状态时，阻断在切换期间流动的电流。

    Single-sided RAM cell and method of accessing same
    4.
    发明授权
    Single-sided RAM cell and method of accessing same 失效
    单面RAM单元及其访问方式

    公开(公告)号：US5877979A

    公开(公告)日：1999-03-02

    申请号：US884369

    申请日：1997-06-26

    申请人： Richard C. Li ,  Hy V. Nguyen ,  Scott S. Nance

    发明人： Richard C. Li ,  Hy V. Nguyen ,  Scott S. Nance

    IPC分类号： G11C11/412 ,  G11C11/00

    CPC分类号： G11C11/412

    摘要： A memory system having a single-sided memory cell, a first voltage supply terminal and a control circuit is provided. The single-sided memory cell has a first node and a second node. Data values are written to the memory cell by selectively applying data signals to the first node or the second node, and data values are read from the memory cell from the second node. The control circuit is coupled to receive a data signal having one of a first state and a second state. The control circuit couples the first node of the memory cell to the first voltage supply terminal when the data signal is in the first state, thereby writing a first data value to the memory cell. The control circuit couples the second node of the memory cell to the first voltage supply terminal when the data signal is in the second state, thereby writing a second data value to the memory cell. Because the first voltage supply terminal is used to write both the first and second data values to the memory cell, problems associated with inadequate write voltages are eliminated by appropriate selection of the first supply voltage.

    摘要翻译： 提供具有单面存储单元，第一电压供应端子和控制电路的存储器系统。 单面存储单元具有第一节点和第二节点。 通过选择性地将数据信号应用于第一节点或第二节点，将数据值写入存储器单元，并且从第二节点从存储器单元读取数据值。 控制电路被耦合以接收具有第一状态和第二状态之一的数据信号。 当数据信号处于第一状态时，控制电路将存储单元的第一节点耦合到第一电压提供端，从而将第一数据值写入存储单元。 当数据信号处于第二状态时，控制电路将存储单元的第二节点耦合到第一电压供应端，从而将第二数据值写入存储单元。 因为第一电压供应端用于将第一和第二数据值写入存储单元，所以通过适当地选择第一电源电压来消除与写入电压不足有关的问题。

    Output driver with reduced ground bounce
    5.
    发明授权
    Output driver with reduced ground bounce 失效
    输出驱动器减少地面反弹

    公开(公告)号：US6118324A

    公开(公告)日：2000-09-12

    申请号：US884822

    申请日：1997-06-30

    申请人： Richard C. Li ,  Hy V. Nguyen

    发明人： Richard C. Li ,  Hy V. Nguyen

    IPC分类号： H03K17/16

    CPC分类号： H03K17/164

    摘要： An output driver circuit including a first path from an output pad to ground through a first switch, and a second path from the output pad to ground through series-connected second and third switches. The first switch is directly connected to a pull-down signal source, and one of the second and third switches is connected to the pull-down signal source through a one-shot circuit. In a pull-up state, the first and second switches are opened, and the one-shot circuit generates a stabilized output signal which closes the third switch. When the output driver circuit switches to a pull-down state, the first switch is closed, thereby connecting the output pad to ground via the first path. The signal change also closes the second switch. In addition, due to a propagation delay of the second signal through the one-shot circuit, the third switch initially remains closed, thereby also connecting the output pad to ground via the second path. The one-shot circuit then opens the third switch before the output pad fully discharges. Subsequently, the one-shot circuit returns to its stabilized state and closes the third switch, thereby connecting the substantially fully discharged output pad to ground through both the first and second paths.

    摘要翻译： 一种输出驱动器电路，包括从第一开关从输出焊盘到接地的第一路径，以及通过串联连接的第二和第三开关从输出焊盘到接地的第二路径。 第一开关直接连接到下拉信号源，第二和第三开关之一通过单触发电路连接到下拉信号源。 在上拉状态下，第一和第二开关断开，单向电路产生稳定的输出信号，其闭合第三开关。 当输出驱动器电路切换到下拉状态时，第一开关闭合，从而通过第一路径将输出焊盘连接到地。 信号变化也关闭第二个开关。 此外，由于通过单触发电路的第二信号的传播延迟，第三开关最初保持闭合，从而也通过第二路径将输出焊盘连接到地。 然后，单触发电路在输出焊盘完全放电之前打开第三个开关。 随后，单触发电路恢复到其稳定状态并关闭第三开关，从而通过第一和第二路径将基本完全放电的输出焊盘连接到地。

    Selectively decoupled I/O latch
    6.
    发明授权
    Selectively decoupled I/O latch 失效
    选择性去耦I / O锁存器

    公开(公告)号：US5828608A

    公开(公告)日：1998-10-27

    申请号：US756619

    申请日：1996-11-26

    申请人： Hy V. Nguyen ,  Richard C. Li

    发明人： Hy V. Nguyen ,  Richard C. Li

    IPC分类号： G11C7/10 ,  G11C8/06 ,  G11C7/00

    CPC分类号： G11C8/06 ,  G11C7/1051

    摘要： A selectively decoupled latch circuit used for latching a signal. The circuit contains an input line for accepting an input signal to the circuit. A latch is connected to the input line for latching the input signal. A transfer gate is also connected to the input line and latch for transferring the input signal to the latch according to a clock signal. A transistor is connected in a series with a feedback loop associated with the latch. The transistor selectively decouples the feedback path according to the clock signal. By selectively decoupling the feedback path, it is easier for a new input signal to become latched because contention between a prior latched signal versus the new input signal is minimized. An output line is connected to the latch for outputting a latched signal.

    摘要翻译： 用于锁存信号的选择性去耦锁存电路。 电路包含用于接受电路的输入信号的输入线。 锁存器连接到输入线，用于锁存输入信号。 传输门也连接到输入线和锁存器，用于根据时钟信号将输入信号传送到锁存器。 晶体管与与锁存器相关联的反馈回路串联连接。 晶体管根据时钟信号选择性地去耦反馈路径。 通过选择性地去耦合反馈路径，由于先前锁存的信号与新的输入信号之间的争用被最小化，所以更容易使新的输入信号被锁存。 输出线连接到锁存器，用于输出锁存信号。

    Input buffer having an accelerated signal transition
    7.
    发明授权
    Input buffer having an accelerated signal transition 失效
    具有加速信号转换的输入缓冲器

    公开(公告)号：US5410189A

    公开(公告)日：1995-04-25

    申请号：US128387

    申请日：1993-09-27

    申请人： Hy V. Nguyen

    发明人： Hy V. Nguyen

    IPC分类号： H03K19/017 ,  H03K5/12

    CPC分类号： H03K19/01721

    摘要： A CMOS buffer includes an input inverter, and a pull-up circuit coupled to the input inverter. The pull-up circuit provides an additional, temporary, signal pull-up on the output terminal of the input inverter during a high to low signal transition on its input terminal. The pull-up circuit includes a means for creating a signal delay. In one embodiment, the means for creating a signal delay includes a second and third inverter in series, the second inverter receiving an output signal from the input inverter. The pull-up circuit further includes two transistors for transferring a high signal to an output line of the input inverter. One transistor is controlled by a signal transferred by the means for creating a delay. The other transistor is controlled by an input signal to the input inverter. This pull-up circuit configuration ensures that the signal transition from low to high is substantially equal to the signal transition from high to low on the output line of the input inverter. The input inverter is then coupled to a driving circuit inverter to provide a CMOS buffer configuration.

    摘要翻译： CMOS缓冲器包括输入反相器和耦合到输入反相器的上拉电路。 上拉电路在输入端子的高电平至低信号转换期间，在输入反相器的输出端子上提供额外的临时信号上拉。 上拉电路包括用于产生信号延迟的装置。 在一个实施例中，用于产生信号延迟的装置包括串联的第二和第三反相器，第二反相器接收来自输入反相器的输出信号。 上拉电路还包括用于将高信号传送到输入反相器的输出线的两个晶体管。 一个晶体管由通过用于产生延迟的装置传送的信号控制。 另一个晶体管由输入反相器的输入信号控制。 该上拉电路配置确保从低电平到高电平的信号转换基本上等于输入逆变器的输出线上从高电平到低电平的信号转换。 然后将输入反相器耦合到驱动电路逆变器以提供CMOS缓冲器配置。

    Fast signal path for programmable logic device
    9.
    发明授权
    Fast signal path for programmable logic device 失效
    可编程逻辑器件的快速信号通路

    公开(公告)号：US5719506A

    公开(公告)日：1998-02-17

    申请号：US533884

    申请日：1995-09-26

    申请人： Sholeh Diba ,  Hy V. Nguyen

    发明人： Sholeh Diba ,  Hy V. Nguyen

    IPC分类号： H03K19/177 ,  H03K7/38 ,  H03K19/0175

    CPC分类号： H03K19/17736 ,  H03K19/17704 ,  H03K19/17792

    摘要： Propagation delay along a signal path in a programmable logic device is reduced by providing improved switching and buffering along the device signal path. Such improvement is achieved by providing a separate buffer for each signal path leading from a given device input pad. In this manner, the buffer is smaller without increasing net power consumption. Improved output drivers are also provided in which device sizes are optimized to sink/source larger amounts of current, thereby improving device speed. A feedback arrangement, including a bootstrap device, provides a path that augments the current provided within the output buffer, thereby assisting a low to high signal transition. An improved OR gate is also provided that precharges a gate output line to ensure fast state transition, while eliminating the need for complementary gate switching logic.

    摘要翻译： 通过沿设备信号路径提供改进的切换和缓冲来减少可编程逻辑器件中的信号路径的传播延迟。 通过为从给定的设备输入板引出的每个信号路径提供单独的缓冲器来实现这种改进。 以这种方式，缓冲器较小，而不增加净功率消耗。 还提供了改进的输出驱动器，其中设备尺寸被优化以吸收/输出更大量的电流，从而提高设备速度。 包括自举装置的反馈装置提供增加输出缓冲器内提供的电流的路径，从而辅助低到高的信号转换。 还提供了改进的或门，其预充电栅极输出线以确保快速状态转换，同时不需要互补栅极开关逻辑。

    High-speed tristate inverter
    10.
    发明授权
    High-speed tristate inverter 失效
    高速三态变频器

    公开(公告)号：US5399925A

    公开(公告)日：1995-03-21

    申请号：US101131

    申请日：1993-08-02

    申请人： Hy V. Nguyen

    发明人： Hy V. Nguyen

    IPC分类号： H03K19/094 ,  H03K19/00 ,  H03K19/0175

    CPC分类号： H03K19/09429

    摘要： The tristate inverter of the present invention includes an input line, an output line, a first transistor for transferring a high signal to the output line, and a second transistor for transferring a low signal to the output line. The tristate inverter further includes means for isolating the input line from the second transistor, thereby significantly improving the rise time of the signal on the output line.

    摘要翻译： 本发明的三态反相器包括输入线，输出线，用于将高信号传送到输出线的第一晶体管，以及用于将低信号传送到输出线的第二晶体管。 三态反相器还包括用于将输入线与第二晶体管隔离的装置，从而显着地改善输出线上信号的上升时间。