公开(公告)号：USRE38388E1

公开(公告)日：2004-01-13

申请号：US09882444

申请日：2001-06-14

申请人： Nitin V. Sarangdhar ,  Konrad K. Lai ,  Gurbir Singh ,  Peter D. MacWilliams ,  Stephen S. Pawlowski ,  Michael W. Rhodehamel

发明人： Nitin V. Sarangdhar ,  Konrad K. Lai ,  Gurbir Singh ,  Peter D. MacWilliams ,  Stephen S. Pawlowski ,  Michael W. Rhodehamel

IPC分类号： H04L12417

CPC分类号： G06F13/368 ,  G06F13/4213

摘要： A method and apparatus of performing bus transactions on the bus of the computer system. The present invention includes a method and apparatus for permitting out-of-order replies in a pipelined bus system. The out-of-order responses include the sending of tokens between both the requesting agents and the responding agents in the computer system without the use of dedicated token buses.

公开(公告)号：US5809524A

公开(公告)日：1998-09-15

申请号：US822044

申请日：1997-03-24

申请人： Gurbir Singh ,  Wen-Hann Wang ,  Michael W. Rhodehamel ,  John M. Bauer ,  Nitin V. Sarangdhar

发明人： Gurbir Singh ,  Wen-Hann Wang ,  Michael W. Rhodehamel ,  John M. Bauer ,  Nitin V. Sarangdhar

IPC分类号： G06F12/08 ,  G06F12/12

CPC分类号： G06F12/123 ,  G06F12/0831

摘要： A method and apparatus for cache memory replacement line identification have a cache interface which provides a communication interface between a cache memory and a controller for the cache memory. The interface includes an address bus, a data bus, and a status bus. The address bus transfers requested addresses from the controller to the cache memory. The data bus transfers data associated with requested addresses from the controller to the cache memory, and also transfers replacement line addresses from the cache memory to the controller. The status bus transfers status information associated with the requested addresses from the cache memory to the controller which indicate whether the requested addresses are contained in the cache memory. In one embodiment, the data bus also transfers cache line data associated with a requested address from the cache memory to the controller when the requested address hits the cache memory.

摘要翻译： 一种用于高速缓存存储器替代线路识别的方法和装置具有缓存接口，其提供高速缓冲存储器和用于高速缓冲存储器的控制器之间的通信接口。 该接口包括地址总线，数据总线和状态总线。 地址总线将请求的地址从控制器传送到高速缓冲存储器。 数据总线将与请求的地址相关联的数据从控制器传送到高速缓冲存储器，并且还将替换行地址从高速缓冲存储器传送到控制器。 状态总线将与请求的地址相关联的状态信息从高速缓冲存储器传送到控制器，该控制器指示所请求的地址是否包含在高速缓冲存储器中。 在一个实施例中，当请求的地址与高速缓冲存储器匹配时，数据总线还将与所请求的地址相关联的高速缓存行数据从高速缓冲存储器传送到控制器。

公开(公告)号：US5796977A

公开(公告)日：1998-08-18

申请号：US688238

申请日：1996-07-29

申请人： Nitin V. Sarangdhar ,  Gurbir Singh ,  Konrad Lai ,  Stephen S. Pawlowski ,  Peter D. MacWilliams ,  Michael W. Rhodehamel

发明人： Nitin V. Sarangdhar ,  Gurbir Singh ,  Konrad Lai ,  Stephen S. Pawlowski ,  Peter D. MacWilliams ,  Michael W. Rhodehamel

IPC分类号： G06F12/08 ,  G06F13/18 ,  G06F12/00 ,  G06F13/00

CPC分类号： G06F13/18 ,  G06F12/0831

摘要： A computer system incorporating a pipelined bus that maintains data coherency, supports long latency transactions and provides processor order is described. The computer system includes bus agents having in-order-queues that track multiple outstanding transactions across a system bus and that perform snoops in response to transaction requests providing snoop results and modified data within one transaction. Additionally, the system supports long latency transactions by providing deferred identifiers during transaction requests that are used to restart deferred transactions.

摘要翻译： 描述了包含维护数据一致性的流水线总线的计算机系统，支持长延迟事务并提供处理器顺序。 计算机系统包括总线代理，其具有在系统总线上跟踪多个未完成事务的按顺序队列，并且响应于在一个事务中提供窥探结果和修改的数据的事务请求来执行窥探。 此外，系统通过在用于重新启动延迟事务的事务请求期间提供延迟标识符来支持长延迟事务。

公开(公告)号：US5754833A

公开(公告)日：1998-05-19

申请号：US788356

申请日：1997-01-24

申请人： Gurbir Singh ,  Michael W. Rhodehamel

发明人： Gurbir Singh ,  Michael W. Rhodehamel

IPC分类号： G06F13/42 ,  G06F1/12 ,  G06F13/40 ,  H03K5/135 ,  H03K5/153 ,  H03K5/26 ,  H03L7/183 ,  H04L7/00

CPC分类号： H03K5/26 ,  G06F13/405 ,  H03K5/135 ,  H03K5/153 ,  H03L7/183 ,  H04L7/0012

摘要： An apparatus for synchronously transmitting data between devices operating at different frequencies that have a P/Q integer ratio relationship. The apparatus allows one or more device(s) operating at a high frequency to synchronously exchange data with one or more device(s) operating at a low frequency. The low and high frequencies have a P/Q integer ratio relationship of: low frequency=(P/Q).times.high frequency; where P and Q represent integer values, P is less than Q, and Q is not necessarily an integer multiple of P. A P/Q clock generator generates one or both of the high and low frequency clocks according to the P/Q frequency ratio. An interface controller receives the high frequency clock and the P and Q values as inputs and generates a high-to-low data transfer signal for enabling data transfers from high frequency to low frequency devices. The interface controller also generates a low-to-high frequency data transfer signal for enabling data transfers from low to high frequency devices. The data transfer signals may be used to latch or qualify transfer data during transfer across frequency boundaries. The data transfer signals indicate safe times, or windows, for transferring data across frequency boundaries. A safe time for transferring data across a frequency boundary is a high frequency clock period where the transfer data is stable and the receiving device can receive the data.

摘要翻译： 一种在具有P / Q整数比关系的不同频率工作的设备之间同步发送数据的装置。 该装置允许以高频率操作的一个或多个设备与以低频操作的一个或多个设备同步地交换数据。 低频和高频具有P / Q整数比关系：低频=（P / Q）×高频; 其中P和Q表示整数值，P小于Q，Q不一定是P的整数倍.P / Q时钟发生器根据P / Q频率比产生高频和低频时钟中的一个或两个。 接口控制器接收高频时钟和P和Q值作为输入，并产生高到低的数据传输信号，用于实现从高频到低频器件的数据传输。 接口控制器还产生低到高频数据传输信号，用于实现从低频到高频器件的数据传输。 数据传输信号可用于在跨频率边界传输期间锁存或限定传输数据。 数据传输信号表示跨越频率边界传输数据的安全时间或窗口。 跨频率传输数据的安全时间是传输数据稳定且接收设备可以接收数据的高频时钟周期。

公开(公告)号：US5832534A

公开(公告)日：1998-11-03

申请号：US550777

申请日：1995-10-31

申请人： Gurbir Singh ,  Konrad K. Lai ,  Michael W. Rhodehamel

发明人： Gurbir Singh ,  Konrad K. Lai ,  Michael W. Rhodehamel

IPC分类号： G06F12/08 ,  G06F13/14

CPC分类号： G06F12/0811 ,  G06F12/0897 ,  G06F12/0831 ,  Y02B60/1225

摘要： A method and apparatus for controlling multiple cache memories with a single cache controller. The present invention uses a processor to control the operation of its on-chip level one (L1) cache memory and a level two (L2) cache memory. In this manner, the processor is able to send operations to be performed to the L2 cache memory, such as writing state and/or cache line status to the L2 cache memory. A dedicated bus is coupled between dice. This dedicated bus is used to send control and other signals between the processor and the L2 cache memory.

公开(公告)号：US5701503A

公开(公告)日：1997-12-23

申请号：US360331

申请日：1994-12-21

申请人： Gurbir Singh ,  Wen-Hann Wang ,  Michael W. Rhodehamel ,  John M. Bauer ,  Nitin V. Sarangdhar

发明人： Gurbir Singh ,  Wen-Hann Wang ,  Michael W. Rhodehamel ,  John M. Bauer ,  Nitin V. Sarangdhar

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0897 ,  G06F12/0831

摘要： A method and apparatus for transferring information between a processor and a memory system utilizing a chunk write buffer, where read and write requests to the L2 cache memory are controlled by the processor. The cache line associated with each such request is larger than the interface coupling the L2 cache memory and the processor. Read requests are returned from the L2 cache memory to the processor in burst fashion. Write requests are transferred from the processor to the L2 cache memory during clock cycles in which the processor does not require the interface for a read request. Write requests need not be transferred in burst fashion; rather, a portion of the write request corresponding to the size of the interface, referred to as a chunk, is transferred from the processor to the L2 cache memory and stored temporarily in the chunk write buffer. When the processor has transferred the entire cache line to the L2 cache memory, the processor signals the L2 cache memory to transfer the contents of the chunk write buffer into the data array of the cache memory.

摘要翻译： 一种利用块写入缓冲器在处理器和存储器系统之间传送信息的方法和装置，其中对L2高速缓冲存储器的读取和写入请求由处理器控制。 与每个这样的请求相关联的高速缓存行大于耦合L2高速缓冲存储器和处理器的接口。 读取请求以突发方式从L2高速缓冲存储器返回到处理器。 在处理器不需要读取请求的接口的时钟周期期间，写入请求从处理器传送到L2高速缓冲存储器。 写请求不需要以突发方式传输; 相反，与被称为块的接口的大小相对应的写入请求的一部分从处理器传送到L2高速缓冲存储器，并临时存储在块写入缓冲器中。 当处理器将整个高速缓存行传输到L2高速缓冲存储器时，处理器发信号通知L2缓存存储器，以将块写入缓冲器的内容传送到高速缓冲存储器的数据阵列中。

公开(公告)号：US5615343A

公开(公告)日：1997-03-25

申请号：US302600

申请日：1994-09-08

申请人： Nitin V. Sarangdhar ,  Konrad K. Lai ,  Gurbir Singh ,  Peter D. MacWilliams ,  Stephen S. Pawlowski ,  Michael W. Rhodehamel

发明人： Nitin V. Sarangdhar ,  Konrad K. Lai ,  Gurbir Singh ,  Peter D. MacWilliams ,  Stephen S. Pawlowski ,  Michael W. Rhodehamel

IPC分类号： G06F13/36 ,  G06F13/368 ,  G06F13/37 ,  G06F13/42

CPC分类号： G06F13/37 ,  G06F13/368 ,  G06F13/4213

摘要： A method and apparatus of performing bus transactions on the bus of the computer system. The present invention includes a method and apparatus for permitting out-of-order replies in a pipelined bus system. The out-of-order responses include the sending of tokens between both the requesting agents and the responding agents in the computer system without the use of dedicated token buses.

摘要翻译： 在计算机系统的总线上执行总线事务的方法和装置。 本发明包括一种用于允许流水线总线系统中的无序回复的方法和装置。 无序响应包括在计算机系统中的请求代理和响应代理之间发送令牌，而不使用专用令牌总线。

公开(公告)号：US5715428A

公开(公告)日：1998-02-03

申请号：US639719

申请日：1996-04-29

申请人： Wen-Hann Wang ,  Konrad K. Lai ,  Gurbir Singh ,  Michael W. Rhodehamel ,  Nitin V. Sarangdhar ,  John M. Bauer ,  Mandar S. Joshi ,  Ashwani K. Gupta

发明人： Wen-Hann Wang ,  Konrad K. Lai ,  Gurbir Singh ,  Michael W. Rhodehamel ,  Nitin V. Sarangdhar ,  John M. Bauer ,  Mandar S. Joshi ,  Ashwani K. Gupta

IPC分类号： G06F12/08 ,  G06F13/00

CPC分类号： G06F12/0831 ,  G06F12/0811

摘要： A computer system comprising a plurality of caching agents with a cache hierarchy, the caching agents sharing memory across a system bus and issuing memory access requests in accordance with a protocol wherein a line of a cache has a present state comprising one of a plurality of line states. The plurality of line states includes a modified (M) state, wherein a line of a first caching agent in M state has data which is more recent than any other copy in the system; an exclusive (E) state, wherein a line in E state in a first caching agent is the only one of the agents in the system which has a copy of the data in a line of the cache, the first caching agent modifying the data in the cache line independent of other said agents coupled to the system bus; a shared (S) state, wherein a line in S state indicates that more than one of the agents has a copy of the data in the line; and an invalid (I) state indicating that the line does not exist in the cache. A read or a write to a line in I state results in a cache miss. The present invention associates states with lines and defines rules governing state transitions. State transitions depend on both processor generated activities and activities by other bus agents, including other processors. Data consistency is guaranteed in systems having multiple levels of cache and shared memory and/or multiple active agents, such that no agent ever reads stale data and actions are serialized as needed.

摘要翻译： 一种计算机系统，包括具有高速缓存层级的多个高速缓存代理，所述高速缓存代理器通过系统总线共享存储器并根据协议发出存储器访问请求，其中高速缓存行具有包括多条线路之一的当前状态 状态。 多个行状态包括修改的（M）状态，其中M状态的第一高速缓存代理的行具有比系统中的任何其他副本更新的数据; 排除（E）状态，其中第一高速缓存代理中的E状态中的线是系统中唯一具有高速缓存行中的数据的副本的代理，第一高速缓存代理将数据修改为 所述高速缓存行独立于耦合到所述系统总线的其它所述代理; 共享（S）状态，其中S状态的行指示多于一个代理具有该行中的数据的副本; 和指示该行不存在于缓存中的无效（I）状态。 对I状态的行进行读取或写入会导致高速缓存未命中。 本发明将状态与线相关联并且定义了管理状态转换的规则。 状态转换取决于处理器生成的活动和其他总线代理（包括其他处理器）的活动。 在具有多级缓存和共享内存和/或多个活动代理的系统中保证数据一致性，使得任何代理程序都不会读取过时的数据，并且操作根据需要进行序列化。

公开(公告)号：US5581782A

公开(公告)日：1996-12-03

申请号：US538597

申请日：1995-10-03

申请人： Nitin V. Sarangdhar ,  Konrad K. Lai ,  Gurbir Singh ,  Michael W. Rhodehamel ,  Matthew A. Fisch

发明人： Nitin V. Sarangdhar ,  Konrad K. Lai ,  Gurbir Singh ,  Michael W. Rhodehamel ,  Matthew A. Fisch

IPC分类号： G06F13/36 ,  G06F13/364 ,  H04L12/403 ,  G06F13/18

CPC分类号： G06F13/364 ,  G06F13/36 ,  H04L12/403 ,  H04L12/4015

摘要： A system and method for providing a high performance symmetric arbitration protocol that includes support for priority agents. The bus arbitration protocol supports two classes of bus agents: symmetric agents and priority agents. The symmetric agents support fair, distributed arbitration using a round-robin algorithm. Each symmetric agent has a unique Agent ID assigned at reset. The algorithm arranges the symmetric agents in a circular order of priority. Each symmetric agent also maintains a bus ownership state of busy or idle and a Rotating ID that reflects the symmetric agent with the lowest priority in the next arbitration event. On an arbitration event, the symmetric agent with the highest priority becomes the symmetric owner. However, the symmetric owner is not necessarily the overall bus owner (i.e., a priority agent may be the overall bus owner). The symmetric owner is allowed to take ownership of the bus and issue a transaction on the bus provided no other action of higher priority is preventing the use of the bus. A symmetric owner can maintain ownership without re-arbitrating if the transaction is either a bus-locked or a burst access transaction. The priority agent(s) has higher priority than the symmetric owner. Once the priority agent arbitrates for the bus, it prevents the symmetric owner from issuing any new transactions on the bus unless the new transaction is part of an ongoing bus-locked operation.

摘要翻译： 一种用于提供包括对优先代理的支持的高性能对称仲裁协议的系统和方法。 总线仲裁协议支持两类总线代理：对称代理和优先代理。 对称代理使用循环算法支持公平的分布式仲裁。 每个对称代理都具有在复位时分配的唯一代理ID。 该算法按照循环顺序排列对称代理。 每个对称代理还维持忙或空闲的总线所有权状态以及在下一个仲裁事件中反映具有最低优先级的对称代理的旋转ID。 在仲裁事件中，优先级最高的对称代理成为对称所有者。 然而，对称所有者不一定是总线总线所有者（即，优先代理可以是总线总线所有者）。 允许对称所有者获得公共汽车的所有权，并在公共汽车上发出交易，只要没有更高优先级的其他动作阻止使用公共汽车。 如果事务是总线锁定或突发访问事务，对称所有者可以维护所有权而不重新仲裁。 优先级代理的优先级高于对称所有者。 一旦优先级代理对总线进行仲裁，就可以防止对称所有者在总线上发出任何新的事务，除非新的事务是持续的总线锁定操作的一部分。

公开(公告)号：US4803622A

公开(公告)日：1989-02-07

申请号：US46633

申请日：1987-05-07

申请人： William L. Bain, Jr. ,  Robert C. Bedichek ,  George W. Cox ,  Gerhard Grassl ,  Craig B. Peterson ,  Justin R. Rattner ,  Gurbir Singh ,  Gurbir Singh ,  John L. Wipfli

发明人： William L. Bain, Jr. ,  Robert C. Bedichek ,  George W. Cox ,  Gerhard Grassl ,  Craig B. Peterson ,  Justin R. Rattner ,  Gurbir Singh ,  Gurbir Singh ,  John L. Wipfli

IPC分类号： G06F13/14 ,  G06F13/12 ,  G06F13/38 ,  G06F3/00

CPC分类号： G06F13/124

摘要： An I/O bus sequencer for providing a data path between an execution Unit (EU-10), a register file (14) and devices connected to a bus (28). A programmable logic array (PLA-18) stores a program which controls a service table (20). The service table includes a plurality of entries divided into fields. One of the fields when decoded instructs the PLA as to what kind of operation the bus sequencer is to perform. Line selection (priority) logic (22) connected to I/O request lines (30) and to the service table (20) determines which service table entry the PLA is to use. A bus interface connected to the I/O bus ports (26) and to the PLA (18) routes data between the I/O bus ports (26) and the register file (14), entries of which are controlled by use of register sets. The service table fields include register set descriptors for storing the status of register set buffers. The PLA decodes an ACCESS instruction to start an operation by loading the first register set descriptor, and then decodes sequential SUPPLY instructions to the entry. Each SUPPLY instruction loads an empty register set descriptor field to be used when the current register set descriptor field is exhausted.

摘要翻译： 一种用于在执行单元（EU-10），寄存器文件（14）和连接到总线（28）的设备之间提供数据路径的I / O总线定序器。 可编程逻辑阵列（PLA-18）存储控制服务表（20）的程序。 服务表包括分成字段的多个条目。 解码后的其中一个字段指示PLA对总线音序器执行什么样的操作。 连接到I / O请求线（30）和服务表（20）的线路选择（优先级）逻辑（22）确定PLA要使用的服务表条目。 连接到I / O总线端口（26）和PLA（18）的总线接口在I / O总线端口（26）和寄存器文件（14）之间路由数据，其条目通过使用寄存器 套。 服务表字段包括用于存储寄存器组缓冲器的状态的寄存器集描述符。 PLA通过加载第一个寄存器集描述符对ACCESS指令进行解码以开始操作，然后将顺序的SUPPLY指令解码到该条目。 每个SUPPLY指令加载当前寄存器集描述符字段耗尽时要使用的空寄存器集描述符字段。