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公开(公告)号：US06798953B1
公开(公告)日：2004-09-28
申请号：US09479109
申请日：2000-01-07
申请人： Mitchell S. Cohen , Michael J. Cordes , Steven A. Cordes , William K. Hogan , Glen W. Johnson , Daniel M. Kuchta , Dianne L. Lacey , James L. Speidell , Jeannine M. Trewhella , Joseph P. Zinter
发明人： Mitchell S. Cohen , Michael J. Cordes , Steven A. Cordes , William K. Hogan , Glen W. Johnson , Daniel M. Kuchta , Dianne L. Lacey , James L. Speidell , Jeannine M. Trewhella , Joseph P. Zinter
IPC分类号： G02B630
CPC分类号： G02B6/4246 , G02B6/3652 , G02B6/423 , G02B6/4239
摘要： A structure that includes a substrate, typically a semiconductor chip such as a VCSEL or photodetector chip, and a guide for aligning a signal conveying device, typically an optical fiber, to a transducer such as an optoelectronic device on the semiconductor chip. The guide is formed, in a preferred embodiment, by lithographically exposing and developing a thick layer of photoresist. The structure is assembled by placing and securing the signal conveying device into a cavity-like region of the guide.
摘要翻译： 包括基板，通常为诸如VCSEL或光电检测器芯片的半导体芯片的结构，以及用于将信号传送装置（通常为光纤）对准到诸如半导体芯片上的光电子装置的换能器的引导件。 在优选实施例中，通过光刻曝光和显影厚的光致抗蚀剂层来形成引导件。 通过将信号传送装置放置并固定到引导件的腔状区域来组装结构。
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2.发明授权公开(公告)号：US06350625B1
公开(公告)日：2002-02-26
申请号：US09753272
申请日：2000-12-28
申请人： Mitchell S. Cohen , William K. Hogan , Sudipta K. Ray , James L. Speidell , S. Jay Chey , Steven A. Cordes
发明人： Mitchell S. Cohen , William K. Hogan , Sudipta K. Ray , James L. Speidell , S. Jay Chey , Steven A. Cordes
IPC分类号： H01L2144
CPC分类号： H01L24/11 , H01L33/486 , H01L33/62 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01051 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/30107 , H01S5/02268 , H01S5/02272 , H01S5/02284 , H01S5/183
摘要： A novel optoelectronic packaging submount arrangement which incorporates a 90° C. electrical conductor turn, and more specifically methods of producing optoelectronic packaging submount arrangement incorporating 90° C. electrical conductor turns.
摘要翻译： 一种新颖的光电封装基座装置，其结合了90 C.电导体转弯，更具体地说，制造了包含90 C.电导线的光电封装基座装置的方法
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公开(公告)号：US07915064B2
公开(公告)日：2011-03-29
申请号：US12538515
申请日：2009-08-10
IPC分类号： H01L21/00 , H01L21/311
CPC分类号： H01L21/31051 , B81C1/00611 , B81C2201/0119 , H01L21/0272 , H01L21/0337 , H01L21/31053 , H01L21/31058 , H01L21/3212 , H01L21/76838
摘要： A process for overcoming extreme topographies by first planarizing a cavity in a semiconductor substrate in order to create a planar surface for subsequent lithography processing. As a result of the planarizing process for extreme topographies, subsequent lithography processing is enabled including the deposition of features in close proximity to extreme topographic surfaces (e.g., deep cavities or channels) and, including the deposition of features within a cavity. In a first embodiment, the process for planarizing a cavity in a semiconductor substrate includes the application of dry film resists having high chemical resistance. In a second embodiment, the process for planarizing a cavity includes the filling of cavity using materials such as polymers, spin on glasses, and metallurgy.
摘要翻译： 通过首先平面化半导体衬底中的空腔以便创建用于后续光刻处理的平坦表面来克服极端形貌的过程。 作为极端形貌的平面化处理的结果，可以进行随后的光刻处理，包括紧邻极端地形表面（例如，深空腔或通道）的特征沉积，并且包括在空腔内沉积特征。 在第一实施例中，用于平面化半导体衬底中的腔的方法包括施加具有高耐化学性的干膜抗蚀剂。 在第二实施例中，用于平坦化空腔的方法包括使用诸如聚合物，玻璃旋转和冶金的材料来填充空腔。
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公开(公告)号：US20110130005A1
公开(公告)日：2011-06-02
申请号：US13024711
申请日：2011-02-10
IPC分类号： H01L21/3105
CPC分类号： H01L21/31051 , B81C1/00611 , B81C2201/0119 , H01L21/0272 , H01L21/0337 , H01L21/31053 , H01L21/31058 , H01L21/3212 , H01L21/76838
摘要： A process for overcoming extreme topographies by first planarizing a cavity in a semiconductor substrate in order to create a planar surface for subsequent lithography processing. As a result of the planarizing process for extreme topographies, subsequent lithography processing is enabled including the deposition of features in close proximity to extreme topographic surfaces (e.g., deep cavities or channels) and, including the deposition of features within a cavity. In a first embodiment, the process for planarizing a cavity in a semiconductor substrate includes the application of dry film resists having high chemical resistance. In a second embodiment, the process for planarizing a cavity includes the filling of cavity using materials such as polymers, spin on glasses, and metallurgy.
摘要翻译： 通过首先平面化半导体衬底中的空腔以便创建用于后续光刻处理的平坦表面来克服极端形貌的过程。 作为极端形貌的平面化处理的结果，可以进行随后的光刻处理，包括紧邻极端地形表面（例如，深空腔或通道）的特征沉积，并且包括在空腔内沉积特征。 在第一实施例中，用于平面化半导体衬底中的腔的方法包括施加具有高耐化学性的干膜抗蚀剂。 在第二实施例中，用于平坦化空腔的方法包括使用诸如聚合物，玻璃旋转和冶金的材料来填充空腔。
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公开(公告)号：US20090298292A1
公开(公告)日：2009-12-03
申请号：US12538515
申请日：2009-08-10
IPC分类号： H01L21/3105
CPC分类号： H01L21/31051 , B81C1/00611 , B81C2201/0119 , H01L21/0272 , H01L21/0337 , H01L21/31053 , H01L21/31058 , H01L21/3212 , H01L21/76838
摘要： A process for overcoming extreme topographies by first planarizing a cavity in a semiconductor substrate in order to create a planar surface for subsequent lithography processing. As a result of the planarizing process for extreme topographies, subsequent lithography processing is enabled including the deposition of features in close proximity to extreme topographic surfaces (e.g., deep cavities or channels) and, including the deposition of features within a cavity. In a first embodiment, the process for planarizing a cavity in a semiconductor substrate includes the application of dry film resists having high chemical resistance. In a second embodiment, the process for planarizing a cavity includes the filling of cavity using materials such as polymers, spin on glasses, and metallurgy.
摘要翻译： 通过首先平面化半导体衬底中的空腔以便创建用于后续光刻处理的平坦表面来克服极端形貌的过程。 作为极端形貌的平面化处理的结果，可以进行随后的光刻处理，包括紧邻极端地形表面（例如，深空腔或通道）的特征沉积，并且包括在空腔内沉积特征。 在第一实施例中，用于平面化半导体衬底中的腔的方法包括施加具有高耐化学性的干膜抗蚀剂。 在第二实施例中，用于平坦化空腔的方法包括使用诸如聚合物，玻璃旋转和冶金的材料来填充空腔。
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公开(公告)号：US08603846B2
公开(公告)日：2013-12-10
申请号：US13024711
申请日：2011-02-10
IPC分类号： H01L21/00
CPC分类号： H01L21/31051 , B81C1/00611 , B81C2201/0119 , H01L21/0272 , H01L21/0337 , H01L21/31053 , H01L21/31058 , H01L21/3212 , H01L21/76838
摘要： A process for overcoming extreme topographies by first planarizing a cavity in a semiconductor substrate in order to create a planar surface for subsequent lithography processing. As a result of the planarizing process for extreme topographies, subsequent lithography processing is enabled including the deposition of features in close proximity to extreme topographic surfaces (e.g., deep cavities or channels) and, including the deposition of features within a cavity. In a first embodiment, the process for planarizing a cavity in a semiconductor substrate includes the application of dry film resists having high chemical resistance. In a second embodiment, the process for planarizing a cavity includes the filling of cavity using materials such as polymers, spin on glasses, and metallurgy.
摘要翻译： 通过首先平面化半导体衬底中的空腔以便创建用于后续光刻处理的平坦表面来克服极端形貌的过程。 作为极端形貌的平面化处理的结果，可以进行随后的光刻处理，包括紧邻极端地形表面（例如，深空腔或通道）的特征沉积，并且包括在空腔内沉积特征。 在第一实施例中，用于平面化半导体衬底中的腔的方法包括施加具有高耐化学性的干膜抗蚀剂。 在第二实施例中，用于平坦化空腔的方法包括使用诸如聚合物，玻璃旋转和冶金的材料来填充空腔。
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公开(公告)号：US07784673B2
公开(公告)日：2010-08-31
申请号：US12189388
申请日：2008-08-11
CPC分类号： B23K3/0638 , B23K35/02 , B23K2101/40 , H01L2224/11
摘要： A system and method for injection molding conductive bonding material into a plurality of cavities in a non-rectangular mold is disclosed. The method comprises aligning a fill head with a non-rectangular mold. The non-rectangular mold includes a plurality of cavities. The fill head is placed in substantial contact with the non-rectangular mold. Rotational motion is provided to at least one of the non-rectangular mold and the fill head while the fill head is in substantial contact with the non-rectangular mold. Conductive bonding material is forced out of the fill head toward the non-rectangular mold. The conductive bonding material is provided into at least one cavity of the plurality of cavities contemporaneous with the at least one cavity being in proximity to the fill head.
摘要翻译： 公开了一种用于将导电接合材料注射成非矩形模具中的多个空腔的系统和方法。 该方法包括将填充头与非矩形模具对准。 非矩形模具包括多个空腔。 填充头被放置成与非矩形模具基本接触。 旋转运动提供给非矩形模具和填充头中的至少一个，同时填充头基本上与非矩形模具接触。 将导电接合材料从填充头推向非矩形模具。 导电接合材料被提供到与填充头附近的至少一个空腔同时的多个空腔的至少一个空腔中。
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公开(公告)号：US20080315409A1
公开(公告)日：2008-12-25
申请号：US11765055
申请日：2007-06-19
申请人： Steven A. Cordes , Matthew J. Farinelli , Sherif A. Goma , Peter A. Gruber , John U. Knickerbocker , James L. Speidell
发明人： Steven A. Cordes , Matthew J. Farinelli , Sherif A. Goma , Peter A. Gruber , John U. Knickerbocker , James L. Speidell
IPC分类号： H01L23/48
CPC分类号： H01L21/6835 , H01L24/11 , H01L24/81 , H01L24/83 , H01L24/97 , H01L25/0652 , H01L25/0655 , H01L25/50 , H01L2224/0401 , H01L2224/06183 , H01L2224/11003 , H01L2224/11334 , H01L2224/13099 , H01L2224/16137 , H01L2224/16238 , H01L2224/17183 , H01L2224/81005 , H01L2224/811 , H01L2224/81191 , H01L2224/81192 , H01L2224/8121 , H01L2224/81815 , H01L2224/81986 , H01L2224/97 , H01L2924/00011 , H01L2924/01005 , H01L2924/01006 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01054 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/1532 , H01L2924/30105 , H01L2924/3025 , H01L2924/3512 , H01L2924/00 , H01L2224/83851 , H01L2224/81
摘要： The present invention allows for direct chip-to-chip connections using the shortest possible signal path.
摘要翻译： 本发明允许使用尽可能短的信号路径进行直接芯片到芯片的连接。
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公开(公告)号：US20080272177A1
公开(公告)日：2008-11-06
申请号：US12173346
申请日：2008-07-15
IPC分类号： B23K37/06
CPC分类号： H05K3/3484 , B23K3/0607 , B23K2101/42 , H05K3/4038 , H05K2201/0305 , H05K2201/09472 , H05K2203/0126 , H05K2203/043 , H05K2203/0568
摘要： A system provides solder into cavities in a circuit supporting substrate. The system places a fill head in substantial contact with a circuit supporting substrate. The circuit supporting substrate includes at least one cavity. A linear motion or a rotational motion is provided to at least one of the circuit supporting substrate and the fill head while the fill head is in substantial contact with the circuit supporting substrate. Solder is forced out of the fill head toward the circuit supporting substrate. The solder is provided into the at least one cavity contemporaneous with the at least one cavity being in proximity to the fill head. The system brings a second circuit supporting substrate in close proximity to the circuit supporting substrate, at least one receiving pad on the second circuit supporting substrate substantially contacts the conductive bonding material of the at least one cavity.
摘要翻译： 系统将焊料提供到电路支撑衬底中的空腔中。 该系统使填充头与电路支撑衬底基本接触。 电路支撑衬底包括至少一个空腔。 当填充头与电路支撑衬底基本接触时，向电路支撑衬底和填充头中的至少一个提供直线运动或旋转运动。 焊料被迫从填充头朝向电路支撑基板。 焊料被提供到与填充头附近的至少一个空腔同时的至少一个空腔中。 系统使第二电路支撑衬底紧靠电路支撑衬底，第二电路支撑衬底上的至少一个接收衬垫基本上接触至少一个空腔的导电接合材料。
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公开(公告)号：US07410090B2
公开(公告)日：2008-08-12
申请号：US11409244
申请日：2006-04-21
IPC分类号： B23K31/02
CPC分类号： H05K3/3484 , B23K3/0607 , B23K2101/42 , H05K3/4038 , H05K2201/0305 , H05K2201/09472 , H05K2203/0126 , H05K2203/043 , H05K2203/0568
摘要： A system, method, and apparatus of providing conductive bonding material into a plurality of cavities in a circuit supporting substrate is disclosed. The method comprises placing a fill head in substantial contact with a circuit supporting substrate. The circuit supporting substrate includes at least one cavity. A linear motion or a rotational motion is provided to at least one of the circuit supporting substrate and the fill head while the fill head is in substantial contact with the circuit supporting substrate. Conductive bonding material is forced out of the fill head toward the circuit supporting substrate. The conductive bonding material is provided into the at least one cavity contemporaneous with the at least one cavity being in proximity to the fill head.
摘要翻译： 公开了一种在电路支撑衬底中的多个空腔中提供导电接合材料的系统，方法和装置。 该方法包括将填充头放置成与电路支撑衬底基本接触。 电路支撑衬底包括至少一个空腔。 当填充头与电路支撑衬底基本接触时，向电路支撑衬底和填充头中的至少一个提供直线运动或旋转运动。 导电接合材料被迫从填充头朝向电路支撑基板排出。 所述导电接合材料被提供到与所述至少一个空腔同时的至少一个空腔中，所述至少一个空腔在所述填充头附近。
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