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公开(公告)号：US20160092306A1
公开(公告)日：2016-03-31
申请号：US14498616
申请日：2014-09-26
Applicant: Hewlett-Packard Development Company, L.P.
Inventor： Melvin K. Benedict , Lidia Warnes
IPC: G06F11/10
CPC classification number: G06F11/1076 , G06F11/106
Abstract: An example device in accordance with an aspect of the present disclosure includes a first error corrector to perform platform error correction based on a stride length. A memory includes a second error corrector that is to perform on-memory error correction that is to be disabled for platform error correction.
Abstract translation: 根据本公开的一个方面的示例性装置包括：第一误差校正器，用于基于步幅长度执行平台误差校正。 存储器包括第二错误校正器，其将执行对于平台错误校正被禁用的存储器内部错误校正。
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公开(公告)号：US20160085691A1
公开(公告)日：2016-03-24
申请号：US14778341
申请日：2013-03-28
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Inventor： Melvin K. Benedict , William James Walker , Andrew C. Walton
CPC classification number: G06F12/123 , G06F12/0806 , G06F12/0888 , G06F12/0891 , G06F2212/1021 , G06F2212/1032 , G06F2212/22 , G06F2212/502 , G06F2212/604
Abstract: A technique includes monitoring activation rates of a plurality of memory locations associated with a plurality of memory addresses and regulating the activation rates. The regulating includes selectively updating a cache with the memory addresses based on the activation rates.
Abstract translation: 一种技术包括监视与多个存储器地址相关联的多个存储器位置的激活速率并调节激活速率。 调节包括基于激活速率选择性地更新具有存储器地址的高速缓存。
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公开(公告)号：US20160077751A1
公开(公告)日：2016-03-17
申请号：US14787673
申请日：2013-04-30
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Inventor： Melvin K. Benedict
IPC: G06F3/06
CPC classification number: G06F3/0619 , G06F3/0622 , G06F3/0659 , G06F3/0673 , G06F13/1626 , G06F13/1631 , G11C2207/2272
Abstract: A computing system can include a processor and a memory. The computing system can also include a memory controller to interface between the processor and the memory. The memory controller coalesces requests to access a memory row to form a single request to access the memory row.
Abstract translation: 计算系统可以包括处理器和存储器。 计算系统还可以包括存储器控制器以在处理器和存储器之间进行接口。 存储器控制器合并访问存储器行的请求，以形成访问存储器行的单个请求。
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Patent Agency Ranking
公开(公告)号：US09442801B2
公开(公告)日：2016-09-13
申请号：US14498616
申请日：2014-09-26
Applicant: Hewlett-Packard Development Company, L.P.
Inventor： Melvin K. Benedict , Lidia Warnes
CPC classification number: G06F11/1076 , G06F11/106
Abstract: An example device includes a first error corrector to perform platform error correction based on a stride length. A memory includes a second error corrector that is to perform on-memory error correction that is to be disabled for platform error correction.
Abstract translation: 示例性装置包括第一误差校正器，用于基于步幅长度来执行平台纠错。 存储器包括第二错误校正器，其将执行对于平台错误校正被禁用的存储器内部错误校正。
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公开(公告)号：US20140359181A1
公开(公告)日：2014-12-04
申请号：US13906375
申请日：2013-05-31
Applicant: Hewlett-Packard Development Company, L.P.
Inventor： Melvin K. Benedict
IPC: G06F13/16
CPC classification number: G06F13/1689
Abstract: A technique includes delaying bus activity targeting a memory device and indicating a command for the memory device to allow time for the memory device to complete processing the command. The delaying of the bus activity includes selectively generating an error signal on a memory bus.
Abstract translation: 一种技术包括延迟针对存储器设备的总线活动，并指示存储器设备的命令以允许存储器设备的时间来完成对命令的处理。 总线活动的延迟包括在存储器总线上选择性地产生误差信号。
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公开(公告)号：US20160124797A1
公开(公告)日：2016-05-05
申请号：US14889973
申请日：2013-06-27
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Inventor： Melvin K. Benedict
IPC: G06F11/07
CPC classification number: G06F11/0772 , G06F11/073 , G06F11/0751 , G06F11/079 , G06F11/1004 , G06F11/1405 , G06F11/141 , G06F13/1689 , G06F13/1694 , G11B20/10222
Abstract: A technique includes receiving, by a device a command, wherein a response to the command is expected from the device within a predetermined response time. The device may selectively generate an error signal to allow time for the device to complete processing the command.
Abstract translation: 一种技术包括由设备接收命令，其中在预定响应时间期间期望从该设备对该命令的响应。 该设备可以选择性地产生错误信号，以允许设备完成处理该命令的时间。
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公开(公告)号：US20160103726A1
公开(公告)日：2016-04-14
申请号：US14894220
申请日：2013-05-31
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Inventor： Melvin K. Benedict , Andrew C. Walton , Lidia Warnes
IPC: G06F11/07
CPC classification number: G06F11/079 , G06F3/0619 , G06F11/073 , G06F11/0751 , G06F11/076 , G06F11/0787 , G06F11/1004
Abstract: A technique includes accessing error information generated in response to memory errors of a memory device. The error information generated in response to the memory errors of the memory device may then be determined as indicative of a row hammer error for the memory device.
Abstract translation: 一种技术包括访问响应于存储器设备的存储器错误而生成的错误信息。 然后可以将响应于存储器件的存储器错误而产生的错误信息确定为指示存储器件的行锤错误。
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公开(公告)号：US20150004824A1
公开(公告)日：2015-01-01
申请号：US13931286
申请日：2013-06-28
Applicant: Hewlett-Packard Development Company, L.P.
Inventor： Vincent Nguyen , Binh Nguyen , Melvin K. Benedict , Minh H. Nguyen
IPC: H01R13/629 , G01R31/04
CPC classification number: G01R31/041 , H01R12/7029 , H01R13/641
Abstract: The present disclosure describes, in one example, a dual inline memory module socket. The dual inline memory module socket includes a base to receive a memory module. The base further comprises a first detection pin and a second detection pin. A latch may be coupled to the base and is to electrically couple the first detection pin to the second detection pin in a dosed position to enable a determination that the memory module is properly seated.
Abstract translation: 本公开在一个示例中描述了双列直插存储器模块插座。 双列直插式内存模块插座包括一个接收内存模块的基座。 基座还包括第一检测引脚和第二检测引脚。 闩锁可以联接到基座并且将电子耦合到处于计量位置的第一检测销到第二检测销，以使得可以确定存储器模块正确就位。
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