公开(公告)号：US20240385960A1

公开(公告)日：2024-11-21

申请号：US18368502

申请日：2023-09-14

Applicant: Hitachi, Ltd.

Inventor： Katsuya TANAKA ,  Kentaro SHIMADA

IPC: G06F12/02 ,  G06F13/16 ,  G06F13/18 ,  G06F13/40

Abstract: A frontend interface of a controller according to the present invention includes a plurality of corresponding queueing interfaces for each processor of the controller, and an enqueueing destination of a host I/O command can be switched in response to an instruction from a processor. When a controller OS restarts, the controller waits for completion of a host I/O and executes controller blocking and restarting during setup. Therefore, to determine whether or not this process is possible, the processor gives an instruction to switch a queue and waits until a switch source queue is empty.

公开(公告)号：US20230008395A1

公开(公告)日：2023-01-12

申请号：US17691162

申请日：2022-03-10

Applicant: Hitachi, Ltd.

Inventor： Yutaro KOBAYASHI ,  Katsuya TANAKA ,  Hideaki FUKUDA ,  Yoshikazu MURAYAMA

IPC: G06F3/06 ,  G06F13/16

Abstract: Each storage controller comprises a first storage unit, an interface unit, and a processing unit which sends, to the interface unit, a parameter which instructs n-fold write of writing data in each of n-number of (n is a natural number of 2 or more) other storage controllers. When the interface unit receives the parameter, the interface unit executes each processing of acquiring the data from the first storage unit and storing the data in the second storage unit, generating n-number of requests of writing the data in each of n-number of the other storage controllers, storing each of the generated requests in n-number of the queues corresponding to each of n-number of the other storage controllers, and processing each request stored in each queue and transferring the data stored in the second storage unit to each of n-number of the other storage controllers.

公开(公告)号：US20180011763A1

公开(公告)日：2018-01-11

申请号：US15545451

申请日：2015-02-26

Applicant: Hitachi, Ltd.

Inventor： Katsuya TANAKA ,  Makio MIZUNO

IPC: G06F11/10 ,  G06F3/06 ,  G06F17/30

CPC classification number: G06F11/1076 ,  G06F3/0605 ,  G06F3/0635 ,  G06F11/0727 ,  G06F11/0757 ,  G06F13/10 ,  G06F16/172 ,  G06F16/1827

Abstract: A storage device according to an embodiment of the present invention has a plurality of storage nodes, each of which has a plurality of logical ports having send and receive queues for a communication request and an identification number, and an internal network for connecting the plurality of storage nodes with one another. The storage nodes each have, as the logical ports, a data communication logical port used for data communication with other storage nodes and an error communication logical port used to notify the other storage nodes of a state of the data communication logical port. When detecting an occurrence of transition of the data communication logical port to an error state, the storage node uses the error communication logical port to notify the other storage nodes of the identification number and the state of the data communication logical port.

公开(公告)号：US20220337532A1

公开(公告)日：2022-10-20

申请号：US17462425

申请日：2021-08-31

Applicant: Hitachi, Ltd.

Inventor： Katsuya TANAKA ,  Naoya OKADA

IPC: H04L12/937 ,  H04L12/861 ,  H04L12/931

Abstract: A storage apparatus includes: a plurality of storage controllers including controller interfaces including a plurality of interface ports for connection to the plurality of switches having switch ports, a plurality of virtual networks configured by one of the switch ports is configured in the switch, and the storage controller sends a first packet for specifying the switch port to which the interface port is to be connected from the interface port to the plurality of virtual networks, and determines an address of the interface port used for data transfer between the storage controllers based on a switch number of the switch and a switch port number of the switch port in a case where a second packet including information for specifying the switch number of the switch and the switch port number of the switch port to which the interface port is to be connected is received.

公开(公告)号：US20230315345A1

公开(公告)日：2023-10-05

申请号：US17947811

申请日：2022-09-19

Applicant: Hitachi, Ltd.

Inventor： Katsuya TANAKA ,  Yutaro KOBAYASHI ,  Hideaki FUKUDA

IPC: G06F3/06

CPC classification number: G06F3/0683 ,  G06F3/0604 ,  G06F3/0655

Abstract: A storage apparatus includes a plurality of storage controllers. Each of the plurality of storage controllers includes a controller interface for connecting the storage controllers. The controller interface includes one or more logical ports corresponding to each storage controller of the connection destination. When converting the first request of the first protocol used in the storage controller into the second request of the second protocol used in the inter-storage controller network, the controller interface stores the identification information of the first request and the identification information of the second request in the send queue of the logical port.

公开(公告)号：US20170177485A1

公开(公告)日：2017-06-22

申请号：US15126006

申请日：2014-07-11

Applicant: HITACHI, LTD.

Inventor： Makio MIZUNO ,  Norio SHIMOZONO ,  Katsuya TANAKA

IPC: G06F12/0868 ,  H04L29/08 ,  G06F3/06

CPC classification number: G06F12/0868 ,  G06F3/06 ,  G06F3/0601 ,  G06F3/0604 ,  G06F3/0658 ,  G06F3/067 ,  G06F12/0806 ,  G06F2212/284 ,  H04L67/1097

Abstract: A storage system includes a plurality of controllers each including a processor module and a memory, and a relay unit to relay a communication between the processor modules. The relay unit executes assignment determination to determine one of the processor module of a first controller and the processor module of a second controller is a processor module processing a command stored in the memory. The first controller includes memory storing the command, and the second controller is any of the controllers other than the first controller. When the relay unit determines the command of the processor module of the first controller, the relay unit notifies storage location information of the command to the processor module of the first controller, and when the relay unit determines the command to be processed by the processor module of the second controller, the relay unit transfer the command to the second controller.

公开(公告)号：US20150317272A1

公开(公告)日：2015-11-05

申请号：US14650996

申请日：2013-01-23

Applicant: HITACHI, LTD

Inventor： Katsuya TANAKA ,  Masanori TAKADA ,  Naoya OKADA

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4081 ,  G06F13/385 ,  G06F13/4022 ,  G06F13/4221 ,  G06F2213/0026 ,  G06F2213/3802 ,  G06F2213/3804

Abstract: In a storage subsystem adopting HDD and PCIe-SSD as storage media, as a method for preventing the complication of having to select a removal method while considering the drive type inserted to the drive slot since the method for removing the HDD differs from the method for removing the PCIe-SSD according to the prior art, the present invention provides an LED for displaying whether it is possible to remove the HDD or the PCIe-SSD inserted to the slot of a drive enclosure, wherein when an HDD is inserted in the drive slot, the LED displays that removal of the HDD is enabled when power supply to the HDD is stopped, and when PCIe-SSD is inserted to the drive slot, the LED displays that removal of the SSD is enabled when Downstream Port Containment (DPC) is triggered in the downstream port of the PCIe switch to which the SSD is connected.

Abstract translation: 在采用HDD和PCIe-SSD作为存储介质的存储子系统中，作为防止在考虑插入到驱动器槽的驱动类型的同时选择拆卸方法的复杂性的方法，因为用于移除HDD的方法与用于 根据现有技术移除PCIe-SSD，本发明提供了一种LED，用于显示是否可以移除插入到驱动器机箱的槽中的HDD或PCIe-SSD，其中当将HDD插入驱动器中时 插槽时，LED显示屏停止HDD供电，并且当PCIe-SSD插入驱动器插槽时，LED显示，当下游端口遏制（DPC） 在与SSD连接的PCIe交换机的下游端口中触发。

公开(公告)号：US20250138943A1

公开(公告)日：2025-05-01

申请号：US18609039

申请日：2024-03-19

Applicant: HITACHI, LTD.

Inventor： Masanori TAKADA ,  Katsuya TANAKA

IPC: G06F11/10 ,  G06F12/0871 ,  G06F12/126

Abstract: In a storage device including a plurality of controllers for controlling data reading and writing operations with respect to at least one host computer, each of the controllers includes: a cache region to which a plurality of management units capable of temporarily storing the data are allocated in accordance with the data reading and writing operations; and a control unit for controlling the data reading and writing operations, and when an error occurs, the control unit determines whether or not an occurrence position of the error is in the cache region, and when it is determined that the occurrence position is in the cache region, the control unit excludes, among the plural management units, a specific management unit that contains the occurrence position from an allocation target in the cache region, to control the data reading and writing operations using remaining management units in the plural management units.

公开(公告)号：US20240406264A1

公开(公告)日：2024-12-05

申请号：US18603641

申请日：2024-03-13

Applicant: Hitachi, Ltd.

Inventor： Tomoki SHOJI ,  Masanori TAKADA ,  Katsuya TANAKA

IPC: H04L67/1097 ,  H04L49/9047

Abstract: A storage system includes a plurality of storage controllers. The storage controller includes a processor, a memory, and a transfer device that processes control data for controlling an internal operation of the storage system, the control data being transmitted and received between the plurality of storage controllers. The processor accumulates the control data in the memory when a transfer request for the control data is generated, generates a write request for transmitting a plurality of the control data stored in the memory, and transmits the write request to the other storage controller. The transfer device writes a plurality of the control data included in the write request to the memory upon receiving the write request.

公开(公告)号：US20210365397A1

公开(公告)日：2021-11-25

申请号：US17010691

申请日：2020-09-02

Applicant: Hitachi, Ltd.

Inventor： Katsuya TANAKA ,  Hirotoshi AKAIKE

IPC: G06F13/40 ,  G06F15/173

Abstract: A storage apparatus in which a controller reads out a port status of a switch in a short period of time is disclosed. The storage apparatus includes a switch and a plurality of storage controllers configured to communicate with each other through the switch. The switch includes a switch processor, a plurality of data ports, a switch integrated circuit, a memory, and a management interface. One of the plurality of data ports and a management port of the management interface are connected to each other. The switch processor stores a status of the plurality of data ports acquired from the switch integrated circuit into the memory. The plurality of storage controllers access the management interface through the plurality of data ports and the management port and receive the statuses of the plurality of data ports stored in the memory from the management interface.