公开(公告)号：US20150295068A1

公开(公告)日：2015-10-15

申请号：US14436892

申请日：2012-10-30

申请人： Haizhou Yin ,  Huilong Zhu ,  Changliang Qin ,  Huaxiang Yin

发明人： Haizhou Yin ,  Huilong Zhu ,  Changliang Qin ,  Huaxiang Yin

IPC分类号： H01L29/66 ,  H01L29/165 ,  H01L29/78 ,  H01L21/265 ,  H01L21/762 ,  H01L29/06 ,  H01L21/306 ,  H01L21/308 ,  H01L29/161 ,  H01L21/02

CPC分类号： H01L29/66636 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/26513 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/3083 ,  H01L21/76224 ,  H01L29/0653 ,  H01L29/161 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7848

摘要： Provided is a method for manufacturing a MOSFET, including: forming a shallow trench isolation (STI) in a semiconductor substrate to define an active region for the MOSFET; performing etching with the STI as a mask, to expose a surface of the semiconductor substrate, and to protrude a portion of the STI with respect to the surface of the semiconductor substrate, resulting in a protruding portion; forming a first spacer on sidewalls of the protruding portion; forming a gate stack on the semiconductor substrate; forming a second spacer surrounding the gate stack; forming openings in the semiconductor substrate with the STI, the gate stack, the first spacer and the second spacer as a mask; epitaxially growing a semiconductor layer with a bottom surface and sidewalls of each of the openings as a growth seed layer; and performing ion implantation into the semiconductor layer to form source and drain regions.

摘要翻译： 提供一种用于制造MOSFET的方法，包括：在半导体衬底中形成浅沟槽隔离（STI）以限定MOSFET的有源区; 以STI作为掩模进行蚀刻，露出半导体衬底的表面，并且相对于半导体衬底的表面突出STI的一部分，导致突出部分; 在所述突出部分的侧壁上形成第一间隔件; 在半导体衬底上形成栅叠层; 形成围绕所述栅极叠层的第二间隔物; 用STI，栅极叠层，第一间隔物和第二间隔物作为掩模在半导体衬底中形成开口; 外延生长具有每个开口的底表面和侧壁的半导体层作为生长种子层; 并且对半导体层进行离子注入以形成源区和漏区。

公开(公告)号：US09691878B2

公开(公告)日：2017-06-27

申请号：US14436892

申请日：2012-10-30

申请人： Haizhou Yin ,  Huilong Zhu ,  Changliang Qin ,  Huaxiang Yin

发明人： Haizhou Yin ,  Huilong Zhu ,  Changliang Qin ,  Huaxiang Yin

IPC分类号： H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165 ,  H01L21/762 ,  H01L21/02 ,  H01L21/265 ,  H01L21/306 ,  H01L21/308 ,  H01L29/161

CPC分类号： H01L29/66636 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/26513 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/3083 ,  H01L21/76224 ,  H01L29/0653 ,  H01L29/161 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7848

摘要： Provided is a method for manufacturing a MOSFET, including: forming a shallow trench isolation (STI) in a semiconductor substrate to define an active region for the MOSFET; performing etching with the STI as a mask, to expose a surface of the semiconductor substrate, and to protrude a portion of the STI with respect to the surface of the semiconductor substrate, resulting in a protruding portion; forming a first spacer on sidewalls of the protruding portion; forming a gate stack on the semiconductor substrate; forming a second spacer surrounding the gate stack; forming openings in the semiconductor substrate with the STI, the gate stack, the first spacer and the second spacer as a mask; epitaxially growing a semiconductor layer with a bottom surface and sidewalls of each of the openings as a growth seed layer; and performing ion implantation into the semiconductor layer to form source and drain regions.

公开(公告)号：US09548387B2

公开(公告)日：2017-01-17

申请号：US13812941

申请日：2012-08-27

申请人： Huaxiang Yin ,  Changliang Qin ,  Xiaolong Ma ,  Qiuxia Xu ,  Dapeng Chen

发明人： Huaxiang Yin ,  Changliang Qin ,  Xiaolong Ma ,  Qiuxia Xu ,  Dapeng Chen

IPC分类号： H01L27/088 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/66

CPC分类号： H01L29/7848 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0886 ,  H01L29/66818 ,  H01L29/7845 ,  H01L29/785

摘要： The present invention discloses a semiconductor device, comprising a plurality of fins located on a substrate and extending along a first direction; a plurality of gate stack structures extending along a second direction and across each of the fins; a plurality of stress layers located in the fins on both sides of the gate stack structures and having a plurality of source and drain regions therein; a plurality of channel regions located in the fins below the gate stack structures; characterized in that the stress layers have connected parts in the fins and that the channel regions enclose the connected parts.

摘要翻译： 本发明公开了一种半导体器件，包括位于基片上并沿着第一方向延伸的多个翅片; 多个栅极堆叠结构，沿着第二方向延伸并穿过每个所述散热片; 多个应力层，其位于所述栅极叠层结构的两侧的所述鳍片中，并且在其中具有多个源极和漏极区域; 多个通道区域，位于所述栅极叠层结构下方的鳍中; 其特征在于，应力层在翅片中具有连接部分，并且通道区域包围连接部分。

公开(公告)号：US09281398B2

公开(公告)日：2016-03-08

申请号：US14355664

申请日：2012-07-03

申请人： Huaxiang Yin ,  Changliang Qin ,  Xiaolong Ma ,  Qiuxia Xu ,  Dapeng Chen

发明人： Huaxiang Yin ,  Changliang Qin ,  Xiaolong Ma ,  Qiuxia Xu ,  Dapeng Chen

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10

CPC分类号： H01L29/7848 ,  H01L29/1037 ,  H01L29/1095 ,  H01L29/66636 ,  H01L29/7834

摘要： The present invention discloses a semiconductor device, which comprises a substrate, a gate stack structure on the substrate, a channel region in the substrate under the gate stack structure, and source and drain regions at both sides of the channel region, wherein there is a stressed layer under and at both sides of the channel region, in which the source and drain regions are formed. According to the semiconductor device and the method for manufacturing the same of the present invention, a stressed layer is formed at both sides of and under the channel region made of a silicon-based material so as to act on the channel region, thereby effectively increasing the carrier mobility of the channel region and improving the device performance.

摘要翻译： 本发明公开了一种半导体器件，其包括衬底，衬底上的栅极堆叠结构，栅极堆叠结构下的衬底中的沟道区，以及沟道区两侧的源极和漏极区，其中存在 在形成源极和漏极区的沟道区的下侧和两侧具有应力层。 根据本发明的半导体器件及其制造方法，在由硅系材料制成的沟道区域的两侧和下方形成应力层，以作用于沟道区域，从而有效地增加 通道区域的载波移动性和设备性能的提高。

公开(公告)号：US20140027783A1

公开(公告)日：2014-01-30

申请号：US13812867

申请日：2012-08-27

申请人： Huaxiang Yin ,  Changliang Qin ,  Qiuxia Xu ,  Dapeng Chen

发明人： Huaxiang Yin ,  Changliang Qin ,  Qiuxia Xu ,  Dapeng Chen

IPC分类号： H01L21/8234 ,  H01L27/088

CPC分类号： H01L21/823431 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/7853

摘要： The present invention discloses a semiconductor device, comprising a plurality of fins located on a substrate and extending along a first direction; a plurality of gate stack structures extending along a second direction and across each of the fins; a plurality of stress layers located in the fins on both sides of the gate stack structures and having a plurality of source and drain regions therein; a plurality of channel regions located between the plurality of source and drain regions along a first direction; characterized in that the plurality of gate stack structures enclose the plurality of channel regions. In accordance with the semiconductor device and the method of manufacturing the same of the present invention, an all-around nanowire metal multi-gate is formed in self-alignment by punching through and etching the fins at which the channel regions are located using a combination of the hard mask and the dummy gate, thus the device performance is enhanced.

摘要翻译： 本发明公开了一种半导体器件，包括位于基片上并沿着第一方向延伸的多个翅片; 多个栅极堆叠结构，沿着第二方向延伸并穿过每个所述散热片; 多个应力层，其位于所述栅极叠层结构的两侧的所述鳍片中，并且在其中具有多个源极和漏极区域; 沿着第一方向位于所述多个源区和漏区之间的多个沟道区; 其特征在于，所述多个栅极堆叠结构包围所述多个沟道区域。 根据本发明的半导体器件及其制造方法，通过使用组合来对通道区域所在的鳍进行冲压和蚀刻来形成全自动纳米线金属多栅极的自对准 的硬掩模和伪栅极，从而提高了器件性能。

公开(公告)号：US08841190B2

公开(公告)日：2014-09-23

申请号：US13519884

申请日：2012-04-10

申请人： Changliang Qin ,  Huaxiang Yin

发明人： Changliang Qin ,  Huaxiang Yin

IPC分类号： H01L29/872

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/045 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

摘要： This invention relates to a MOS device for making the source/drain region closer to the channel region and a method of manufacturing the same, comprising: providing an initial structure, which includes a substrate, an active region, and a gate stack; performing ion implantation in the active region on both sides of the gate stack, such that part of the substrate material undergoes pre-amorphization to form an amorphous material layer; forming a first spacer; with the first spacer as a mask, performing dry etching, thereby forming a recess, with the amorphous material layer below the first spacer kept; performing wet etching using an etchant solution that is isotropic to the amorphous material layer and whose etch rate to the amorphous material layer is greater than or substantially equal to the etch rate to the {100} and {110} surfaces of the substrate material but is far greater than the etch rate to the {111} surface of the substrate material, thus removing the amorphous material layer below the first spacer, such that the substrate material below the amorphous material layer is exposed to the solution and is etched thereby, and in the end, forming a Sigma shaped recess that extends to the nearby region below the gate stack; and epitaxially forming SiGe in the Sigma shaped recess.

摘要翻译： 本发明涉及一种用于使源极/漏极区域更靠近沟道区域的MOS器件及其制造方法，包括：提供包括衬底，有源区域和栅极堆叠的初始结构; 在栅极堆叠的两侧上的有源区中进行离子注入，使得衬底材料的一部分经历预非晶化以形成无定形材料层; 形成第一间隔物; 以第一间隔物作为掩模，进行干蚀刻，从而形成凹部，保持第一间隔物下面的非晶材料层; 使用对非晶材料层各向同性的蚀刻剂溶液进行湿蚀刻，并且其对非晶材料层的蚀刻速率大于或基本上等于对基板材料的{100}和{110}表面的蚀刻速率，但是 远远大于衬底材料的{111}表面的蚀刻速率，从而去除第一间隔物下方的无定形材料层，使得无定形材料层下面的衬底材料暴露于溶液并被蚀刻，并且在 结束，形成延伸到栅堆叠下方的附近区域的Sigma形凹部; 并在Sigma形凹部中外延形成SiGe。

公开(公告)号：US08716090B2

公开(公告)日：2014-05-06

申请号：US13580962

申请日：2012-06-12

申请人： Changliang Qin ,  Huaxiang Yin

发明人： Changliang Qin ,  Huaxiang Yin

IPC分类号： H01L21/336

CPC分类号： H01L29/165 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

摘要： The present invention provides a manufacturing method for a semiconductor device having epitaxial source/drain regions, in which a diffusion barrier layer of the source/drain regions made of epitaxial silicon-carbon or germanium silicon-carbon are added on the basis of epitaxially growing germanium-silicon of the source/drain regions in the prior art process, and the introduction of the diffusion barrier layer of the source/drain regions prevents diffusion of the dopant in the source/drain regions, thus mitigating the SCE and DIBL effect. The use of the diffusion barrier layer for the source/drain regions can also reduce the dosage of HALO implantation in the subsequent step, thus if HALO is performed before epitaxial growth of the source/drain regions, impact on the surfaces of the source/drain regions can be alleviated; if HALO is performed after epitaxial growth of the source/drain regions, the stress release effect of the epitaxial layer of the source drain/regions caused by the implantation can be reduced as much as possible.

摘要翻译： 本发明提供了一种具有外延源极/漏极区域的半导体器件的制造方法，其中基于外延生长锗添加由外延硅 - 碳或锗硅 - 碳制成的源极/漏极区的扩散阻挡层 在现有技术的工艺中源极/漏极区域的硅，以及源极/漏极区域的扩散阻挡层的引入防止了掺杂剂在源/漏区域中的扩散，从而减轻了SCE和DIBL效应。 用于源极/漏极区域的扩散阻挡层的使用也可以降低后续步骤中的HALO注入的剂量，因此如果在源极/漏极区域的外延生长之前执行HALO，则冲击源极/漏极 地区可以缓解; 如果在源/漏区的外延生长之后执行HALO，则可以尽可能地减少由注入引起的源漏极/区域的外延层的应力释放效应。

公开(公告)号：US20140120719A1

公开(公告)日：2014-05-01

申请号：US13812505

申请日：2012-10-12

申请人： Changliang Qin ,  Huaxiang Yin

发明人： Changliang Qin ,  Huaxiang Yin

IPC分类号： H01L21/3213

CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/28123

摘要： The present invention relates to a method of manufacturing a semiconductor device for improving the spacer mask. In the present invention, a barrier layer and a sacrificial layer are formed, and the portions of the upper part of the spacer whose left and right sides differ greatly are ground away to leave the portion similar to a rectangle at the bottom of the spacer, which is used as the mask to perform the subsequent spacer masking technology. Thus the undesirable influences to the subsequent etching caused by the asymmetric profile of the spacer can be reduced as much as possible.

摘要翻译： 本发明涉及一种制造用于改进间隔掩模的半导体器件的方法。 在本发明中，形成了阻挡层和牺牲层，并且左右两侧的差异较大的间隔物的上部的部分被磨去，使其与垫片底部的长方形相似， 其用作掩模以执行后续间隔物掩蔽技术。 因此，可以尽可能地减少由间隔物的不对称轮廓引起的对随后的蚀刻的不良影响。

公开(公告)号：US20150179797A1

公开(公告)日：2015-06-25

申请号：US14355664

申请日：2012-07-03

申请人： Huaxiang Yin ,  Changliang Qin ,  Xiaolong Ma ,  Qiuxia Xu ,  Dapeng Chen

发明人： Huaxiang Yin ,  Changliang Qin ,  Xiaolong Ma ,  Qiuxia Xu ,  Dapeng Chen

IPC分类号： H01L29/78 ,  H01L29/10 ,  H01L29/66

CPC分类号： H01L29/7848 ,  H01L29/1037 ,  H01L29/1095 ,  H01L29/66636 ,  H01L29/7834

摘要： The present invention discloses a semiconductor device, which comprises a substrate, a gate stack structure on the substrate, a channel region in the substrate under the gate stack structure, and source and drain regions at both sides of the channel region, wherein there is a stressed layer under and at both sides of the channel region, in which the source and drain regions are formed. According to the semiconductor device and the method for manufacturing the same of the present invention, a stressed layer is formed at both sides of and under the channel region made of a silicon-based material so as to act on the channel region, thereby effectively increasing the carrier mobility of the channel region and improving the device performance.

摘要翻译： 本发明公开了一种半导体器件，其包括衬底，衬底上的栅极堆叠结构，栅极堆叠结构下的衬底中的沟道区，以及沟道区两侧的源极和漏极区，其中存在 在形成源极和漏极区的沟道区的下侧和两侧具有应力层。 根据本发明的半导体器件及其制造方法，在由硅系材料制成的沟道区域的两侧和下方形成应力层，以作用于沟道区域，从而有效地增加 通道区域的载波移动性和设备性能的提高。

公开(公告)号：US09006057B2

公开(公告)日：2015-04-14

申请号：US13989164

申请日：2012-07-31

申请人： Changliang Qin ,  Peizhen Hong ,  Huaxiang Yin

发明人： Changliang Qin ,  Peizhen Hong ,  Huaxiang Yin

IPC分类号： H01L21/36 ,  H01L27/088 ,  H01L29/78 ,  H01L21/306 ,  H01L29/66 ,  H01L21/3065 ,  H01L21/265

CPC分类号： H01L21/30604 ,  H01L21/26506 ,  H01L21/30608 ,  H01L21/3065 ,  H01L29/66477 ,  H01L29/66636 ,  H01L29/7848

摘要： A method of manufacturing a semiconductor device is disclosed. In one embodiment, the method comprises: forming a gate stack on a substrate; etching the substrate on both sides of the gate stack to form C-shaped source/drain grooves; and wet-etching the C-shaped source/drain grooves to form Σ-shaped source/drain grooves. With this method, it is possible to effectively increase stress applied to a channel region, to accurately control a depth of the source/drain grooves, and to reduce roughness of side walls and bottom portions of the grooves and thus reduce defects by etching the C-shaped source/drain grooves and then further wet-etching them to form the Σ-shaped source/drain grooves.

摘要翻译： 公开了制造半导体器件的方法。 在一个实施例中，该方法包括：在衬底上形成栅叠层; 在栅极堆叠的两侧蚀刻衬底以形成C形源极/漏极沟槽; 并对C形源极/漏极沟槽进行湿式蚀刻以形成S形的源极/漏极沟槽。 通过该方法，能够有效地增加施加于沟道区域的应力，精确地控制源极/漏极沟槽的深度，并且可以减小沟槽的侧壁和底部的粗糙度，从而通过蚀刻C来减少缺陷 形状的源极/漏极沟槽，然后进一步湿法蚀刻它们以形成源极/漏极沟槽。