公开(公告)号：US08222742B2

公开(公告)日：2012-07-17

申请号：US12457290

申请日：2009-06-05

申请人： Hoo-Sung Cho ,  Han-Soo Kim ,  Jae-Hoon Jang

发明人： Hoo-Sung Cho ,  Han-Soo Kim ,  Jae-Hoon Jang

IPC分类号： H01L23/48

CPC分类号： H01L27/11519 ,  H01L23/481 ,  H01L27/11524 ,  H01L27/11551 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a lower semiconductor layer with first conductive regions and including at least one dummy first conductive region, an upper semiconductor layer with second conductive regions on the lower semiconductor layer and including at least one dummy second conductive region, a penetration hole in the upper semiconductor layer and penetrating the dummy second conductive region and the upper semiconductor layer under the dummy second conductive region, a lower conductive line on the lower semiconductor layer and electrically connected to the first conductive regions, an upper conductive line on the upper semiconductor layer and electrically connected to the second conductive regions, and a first conductive plug in the penetration hole between the lower conductive line and the upper conductive line, the first conductive plug electrically connecting the lower and upper conductive lines and being spaced apart from sidewalls of the penetration hole.

摘要翻译： 半导体器件包括具有第一导电区域并且包括至少一个虚设第一导电区域的下半导体层，在下半导体层上具有第二导电区域的上半导体层，并且包括至少一个虚拟第二导电区域， 上半导体层并且穿过虚设第二导电区域和虚设第二导电区域下的上半导体层，在下半导体层上的下导电线并且电连接到第一导电区域，在上半导体层上的上导电线， 电连接到第二导电区域，以及在下导电线路和上导电线路之间的穿透孔中的第一导电插塞，第一导电插头电连接下导电线路和上导电线路并与穿孔的侧壁间隔开 。

公开(公告)号：US20090315187A1

公开(公告)日：2009-12-24

申请号：US12457290

申请日：2009-06-05

申请人： Hoo-Sung Cho ,  Han-Soo Kim ,  Jae-Hoon Jang

发明人： Hoo-Sung Cho ,  Han-Soo Kim ,  Jae-Hoon Jang

IPC分类号： H01L23/522

CPC分类号： H01L27/11519 ,  H01L23/481 ,  H01L27/11524 ,  H01L27/11551 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a lower semiconductor layer with first conductive regions and including at least one dummy first conductive region, an upper semiconductor layer with second conductive regions on the lower semiconductor layer and including at least one dummy second conductive region, a penetration hole in the upper semiconductor layer and penetrating the dummy second conductive region and the upper semiconductor layer under the dummy second conductive region, a lower conductive line on the lower semiconductor layer and electrically connected to the first conductive regions, an upper conductive line on the upper semiconductor layer and electrically connected to the second conductive regions, and a first conductive plug in the penetration hole between the lower conductive line and the upper conductive line, the first conductive plug electrically connecting the lower and upper conductive lines and being spaced apart from sidewalls of the penetration hole.

摘要翻译： 半导体器件包括具有第一导电区域并且包括至少一个虚设第一导电区域的下半导体层，在下半导体层上具有第二导电区域的上半导体层，并且包括至少一个虚拟第二导电区域， 上半导体层并且穿过虚设第二导电区域和虚设第二导电区域下的上半导体层，在下半导体层上的下导电线并且电连接到第一导电区域，在上半导体层上的上导电线， 电连接到第二导电区域，以及在下导电线路和上导电线路之间的穿透孔中的第一导电插塞，第一导电插头电连接下导电线路和上导电线路并与穿孔的侧壁间隔开 。

公开(公告)号：US20100001337A1

公开(公告)日：2010-01-07

申请号：US12456537

申请日：2009-06-18

申请人： Han-Soo Kim ,  Jae-Hoon Jang ,  Hoo-Sung Cho

发明人： Han-Soo Kim ,  Jae-Hoon Jang ,  Hoo-Sung Cho

IPC分类号： H01L29/792 ,  H01L29/66

CPC分类号： H01L27/11551 ,  H01L27/0207 ,  H01L27/0688

摘要： A semiconductor memory device includes: sequentially stacked first and second semiconductor layers; at least one first memory transistor disposed on the first semiconductor layer; and at least one second memory transistor disposed on the second semiconductor layer, wherein a gate electrode of the first memory transistor has a broader width than that of the second memory transistor.

摘要翻译： 半导体存储器件包括：顺序堆叠的第一和第二半导体层; 设置在所述第一半导体层上的至少一个第一存储晶体管; 以及设置在所述第二半导体层上的至少一个第二存储晶体管，其中所述第一存储晶体管的栅电极具有比所述第二存储晶体管宽的宽度。

公开(公告)号：US20090233405A1

公开(公告)日：2009-09-17

申请号：US12474896

申请日：2009-05-29

申请人： Hoo-Sung Cho ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jong-Hyuk Kim ,  Jae-Hun Jeong ,  Jae-Hoon Jang

发明人： Hoo-Sung Cho ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jong-Hyuk Kim ,  Jae-Hun Jeong ,  Jae-Hoon Jang

IPC分类号： H01L21/336

CPC分类号： H01L27/11524 ,  H01L27/0688 ,  H01L27/11551

摘要： Methods of forming a NAND-type nonvolatile memory device include: forming first common drains and first common sources alternatively in an active region which is defined in a semiconductor substrate and extends one direction, forming a first insulating layer covering an entire surface of the semiconductor substrate, patterning the first insulating layer to form seed contact holes which are arranged at regular distance and expose the active region, forming a seed contact structure filling each of the seed contact holes and a semiconductor layer disposed on the first insulating layer and contacting the seed contact structures, patterning the semiconductor layer to form a semiconductor pattern which extends in the one direction and is disposed over the active region, forming second common drains and second common sources disposed alternatively in the semiconductor pattern in the one direction, forming a second insulating layer covering an entire surface of the semiconductor substrate, forming a source line pattern continuously penetrating the second insulating layer, the semiconductor pattern and the first insulating layer, the source line pattern being connected with the first and second common sources, wherein a grain boundary of the semiconductor layer is positioned at a center between the one pair of seed contact structures adjacent to each other, and is positioned over the first common drain or the first common source.

摘要翻译： 形成NAND型非易失性存储器件的方法包括：在半导体衬底中限定的有源区域中交替形成第一公共漏极和第一公共源，并延伸一个方向，形成覆盖半导体衬底的整个表面的第一绝缘层 图案化第一绝缘层以形成以规则距离布置的暴露有源区域的种子接触孔，形成填充每个种子接触孔的种子接触结构以及设置在第一绝缘层上并接触种子接触的半导体层 结构，图案化所述半导体层以形成在所述一个方向上延伸并设置在所述有源区上方的半导体图案，形成沿所述一个方向交替设置在所述半导体图案中的第二公共漏极和第二公共源，形成第二绝缘层覆盖层 半导体衬底的整个表面 使源极线图案连续地穿过第二绝缘层，半导体图案和第一绝缘层，源极线图案与第一和第二共用源连接，其中半导体层的晶界位于第二绝缘层之间的中心 一对种子接触结构彼此相邻，并且位于第一公共漏极或第一公共源的上方。

公开(公告)号：US07554140B2

公开(公告)日：2009-06-30

申请号：US11651892

申请日：2007-01-10

申请人： Hoo-Sung Cho ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jong-Hyuk Kim ,  Jae-Hun Jeong ,  Jae-Hoon Jang

发明人： Hoo-Sung Cho ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jong-Hyuk Kim ,  Jae-Hun Jeong ,  Jae-Hoon Jang

IPC分类号： H01L31/062

CPC分类号： H01L27/11524 ,  H01L27/0688 ,  H01L27/11551

摘要： Provided is a NAND-type nonvolatile memory device and method of forming the same. In the method, a plurality of cell layers are stacked on a semiconductor substrate. Seed contact holes for forming a semiconductor pattern included in a stacked cell are formed at regular distance. At this time, the seed contact holes are arranged such that a bit line plug or a source line pattern is disposed at a center between one pair of seed contact holes adjacent to each other.

摘要翻译： 提供了一种NAND型非易失性存储器件及其形成方法。 在该方法中，多个单元层层叠在半导体基板上。 用于形成包含在层叠电池中的半导体图案的种子接触孔以规则的距离形成。 此时，种子接触孔布置成使得位线插头或源极线图案设置在彼此相邻的一对种子接触孔之间的中心处。

公开(公告)号：US20080085582A1

公开(公告)日：2008-04-10

申请号：US11651892

申请日：2007-01-10

申请人： Hoo-Sung Cho ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jong-Hyuk Kim ,  Jae-Hun Jeong ,  Jae-Hoon Jang

发明人： Hoo-Sung Cho ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jong-Hyuk Kim ,  Jae-Hun Jeong ,  Jae-Hoon Jang

IPC分类号： H01L21/336

CPC分类号： H01L27/11524 ,  H01L27/0688 ,  H01L27/11551

摘要： Provided is a NAND-type nonvolatile memory device and method of forming the same. In the method, a plurality of cell layers are stacked on a semiconductor substrate. Seed contact holes for forming a semiconductor pattern included in a stacked cell are formed at regular distance. At this time, the seed contact holes are arranged such that a bit line plug or a source line pattern is disposed at a center between one pair of seed contact holes adjacent to each other.

摘要翻译： 提供了一种NAND型非易失性存储器件及其形成方法。 在该方法中，多个单元层层叠在半导体基板上。 用于形成包含在层叠电池中的半导体图案的种子接触孔以规则的距离形成。 此时，种子接触孔布置成使得位线插头或源极线图案设置在彼此相邻的一对种子接触孔之间的中心处。

公开(公告)号：US07709323B2

公开(公告)日：2010-05-04

申请号：US12474896

申请日：2009-05-29

申请人： Hoo-Sung Cho ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jong-Hyuk Kim ,  Jae-Hun Jeong ,  Jae-Hoon Jang

发明人： Hoo-Sung Cho ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jong-Hyuk Kim ,  Jae-Hun Jeong ,  Jae-Hoon Jang

IPC分类号： H01L21/336

CPC分类号： H01L27/11524 ,  H01L27/0688 ,  H01L27/11551

摘要： Methods of forming a NAND-type nonvolatile memory device include: forming first common drains and first common sources alternatively in an active region which is defined in a semiconductor substrate and extends one direction, forming a first insulating layer covering an entire surface of the semiconductor substrate, patterning the first insulating layer to form seed contact holes which are arranged at regular distance and expose the active region, forming a seed contact structure filling each of the seed contact holes and a semiconductor layer disposed on the first insulating layer and contacting the seed contact structures, patterning the semiconductor layer to form a semiconductor pattern which extends in the one direction and is disposed over the active region, forming second common drains and second common sources disposed alternatively in the semiconductor pattern in the one direction, forming a second insulating layer covering an entire surface of the semiconductor substrate, forming a source line pattern continuously penetrating the second insulating layer, the semiconductor pattern and the first insulating layer, the source line pattern being connected with the first and second common sources, wherein a grain boundary of the semiconductor layer is positioned at a center between the one pair of seed contact structures adjacent to each other, and is positioned over the first common drain or the first common source.

摘要翻译： 形成NAND型非易失性存储器件的方法包括：在半导体衬底中限定的有源区域中交替形成第一公共漏极和第一公共源，并延伸一个方向，形成覆盖半导体衬底的整个表面的第一绝缘层 图案化第一绝缘层以形成以规则距离布置的暴露有源区域的种子接触孔，形成填充每个种子接触孔的种子接触结构以及设置在第一绝缘层上并接触种子接触的半导体层 结构，图案化所述半导体层以形成在所述一个方向上延伸并设置在所述有源区上方的半导体图案，形成沿所述一个方向交替设置在所述半导体图案中的第二公共漏极和第二公共源，形成第二绝缘层覆盖层 半导体衬底的整个表面 使源极线图案连续地穿过第二绝缘层，半导体图案和第一绝缘层，源极线图案与第一和第二共用源连接，其中半导体层的晶界位于第二绝缘层之间的中心 一对种子接触结构彼此相邻，并且位于第一公共漏极或第一公共源的上方。

公开(公告)号：US07683404B2

公开(公告)日：2010-03-23

申请号：US11709234

申请日：2007-02-22

申请人： Young-Chul Jang ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Soon-Moon Jung ,  Hoo-Sung Cho ,  Jong-Hyuk Kim

发明人： Young-Chul Jang ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Soon-Moon Jung ,  Hoo-Sung Cho ,  Jong-Hyuk Kim

IPC分类号： H01L25/065

CPC分类号： H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551

摘要： A stacked memory includes at least two semiconductor layers each including a memory cell array. A transistor is formed in a peripheral circuit region of an uppermost semiconductor layer of the at least two semiconductor layers. The transistor is used to operate the memory cell array.

摘要翻译： 堆叠存储器包括至少两个半导体层，每个半导体层包括存储单元阵列。 晶体管形成在至少两个半导体层的最上半导体层的外围电路区域中。 晶体管用于操作存储单元阵列。

公开(公告)号：US07646664B2

公开(公告)日：2010-01-12

申请号：US11869140

申请日：2007-10-09

申请人： Hoo-Sung Cho ,  Soon-Moon Jung ,  Young-Seop Rah ,  Jae-Hoon Jang ,  Jae-Hun Jeong ,  Jun-Beom Park

发明人： Hoo-Sung Cho ,  Soon-Moon Jung ,  Young-Seop Rah ,  Jae-Hoon Jang ,  Jae-Hun Jeong ,  Jun-Beom Park

IPC分类号： G11C8/00

CPC分类号： G11C8/10 ,  G11C8/08 ,  G11C8/14 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1116 ,  H01L27/112 ,  H01L27/11286 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11568

摘要： A semiconductor memory device including a memory cell array, a first row decoder adjacent the memory cell array, and a second row decoder adjacent the memory cell array. A memory cell array may include first and second memory cell blocks on respective first and second semiconductor layers. The first memory cell block may include a first word line coupled to a first row of memory cells on the first semiconductor layer, the second memory cell block may include a second word line coupled to a second row of memory cells on the second semiconductor layer, and the first word line may be between the first and second semiconductor layers. The first row decoder may be configured to control the first word line, and the second row decoder may be configured to control the second word line. A first wiring may electrically connect the first row decoder and the first word line, and a second wiring may electrically connect the second row decoder and the second word line.

摘要翻译： 一种半导体存储器件，包括存储单元阵列，与存储单元阵列相邻的第一行解码器以及与存储单元阵列相邻的第二行解码器。 存储单元阵列可以包括在相应的第一和第二半导体层上的第一和第二存储单元块。 第一存储单元块可以包括耦合到第一半导体层上的第一行存储单元的第一字线，第二存储单元块可以包括耦合到第二半导体层上的第二行存储单元的第二字线， 并且第一字线可以在第一和第二半导体层之间。 第一行解码器可以被配置为控制第一字线，并且第二行解码器可以被配置为控制第二字线。 第一布线可以电连接第一行解码器和第一字线，并且第二布线可电连接第二行解码器和第二字线。

公开(公告)号：US20080084729A1

公开(公告)日：2008-04-10

申请号：US11869140

申请日：2007-10-09

申请人： Hoo-Sung Cho ,  Soon-Moon Jung ,  Young-Seop Rah ,  Jae-Hoon Jang ,  Jae-Hun Jeong ,  Jun-Beom Park

发明人： Hoo-Sung Cho ,  Soon-Moon Jung ,  Young-Seop Rah ,  Jae-Hoon Jang ,  Jae-Hun Jeong ,  Jun-Beom Park

IPC分类号： G11C5/06

CPC分类号： G11C8/10 ,  G11C8/08 ,  G11C8/14 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1116 ,  H01L27/112 ,  H01L27/11286 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11568

摘要： A semiconductor memory device including a memory cell array, a first row decoder adjacent the memory cell array, and a second row decoder adjacent the memory cell array. A memory cell array may include first and second memory cell blocks on respective first and second semiconductor layers. The first memory cell block may include a first word line coupled to a first row of memory cells on the first semiconductor layer, the second memory cell block may include a second word line coupled to a second row of memory cells on the second semiconductor layer, and the first word line may be between the first and second semiconductor layers. The first row decoder may be configured to control the first word line, and the second row decoder may be configured to control the second word line. A first wiring may electrically connect the first row decoder and the first word line, and a second wiring may electrically connect the second row decoder and the second word line.

摘要翻译： 一种半导体存储器件，包括存储单元阵列，与存储单元阵列相邻的第一行解码器以及与存储单元阵列相邻的第二行解码器。 存储单元阵列可以包括在相应的第一和第二半导体层上的第一和第二存储单元块。 第一存储单元块可以包括耦合到第一半导体层上的第一行存储单元的第一字线，第二存储单元块可以包括耦合到第二半导体层上的第二行存储单元的第二字线， 并且第一字线可以在第一和第二半导体层之间。 第一行解码器可以被配置为控制第一字线，并且第二行解码器可以被配置为控制第二字线。 第一布线可以电连接第一行解码器和第一字线，并且第二布线可电连接第二行解码器和第二字线。