公开(公告)号：US07646664B2

公开(公告)日：2010-01-12

申请号：US11869140

申请日：2007-10-09

申请人： Hoo-Sung Cho ,  Soon-Moon Jung ,  Young-Seop Rah ,  Jae-Hoon Jang ,  Jae-Hun Jeong ,  Jun-Beom Park

发明人： Hoo-Sung Cho ,  Soon-Moon Jung ,  Young-Seop Rah ,  Jae-Hoon Jang ,  Jae-Hun Jeong ,  Jun-Beom Park

IPC分类号： G11C8/00

CPC分类号： G11C8/10 ,  G11C8/08 ,  G11C8/14 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1116 ,  H01L27/112 ,  H01L27/11286 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11568

摘要： A semiconductor memory device including a memory cell array, a first row decoder adjacent the memory cell array, and a second row decoder adjacent the memory cell array. A memory cell array may include first and second memory cell blocks on respective first and second semiconductor layers. The first memory cell block may include a first word line coupled to a first row of memory cells on the first semiconductor layer, the second memory cell block may include a second word line coupled to a second row of memory cells on the second semiconductor layer, and the first word line may be between the first and second semiconductor layers. The first row decoder may be configured to control the first word line, and the second row decoder may be configured to control the second word line. A first wiring may electrically connect the first row decoder and the first word line, and a second wiring may electrically connect the second row decoder and the second word line.

摘要翻译： 一种半导体存储器件，包括存储单元阵列，与存储单元阵列相邻的第一行解码器以及与存储单元阵列相邻的第二行解码器。 存储单元阵列可以包括在相应的第一和第二半导体层上的第一和第二存储单元块。 第一存储单元块可以包括耦合到第一半导体层上的第一行存储单元的第一字线，第二存储单元块可以包括耦合到第二半导体层上的第二行存储单元的第二字线， 并且第一字线可以在第一和第二半导体层之间。 第一行解码器可以被配置为控制第一字线，并且第二行解码器可以被配置为控制第二字线。 第一布线可以电连接第一行解码器和第一字线，并且第二布线可电连接第二行解码器和第二字线。

公开(公告)号：US20080084729A1

公开(公告)日：2008-04-10

申请号：US11869140

申请日：2007-10-09

申请人： Hoo-Sung Cho ,  Soon-Moon Jung ,  Young-Seop Rah ,  Jae-Hoon Jang ,  Jae-Hun Jeong ,  Jun-Beom Park

发明人： Hoo-Sung Cho ,  Soon-Moon Jung ,  Young-Seop Rah ,  Jae-Hoon Jang ,  Jae-Hun Jeong ,  Jun-Beom Park

IPC分类号： G11C5/06

CPC分类号： G11C8/10 ,  G11C8/08 ,  G11C8/14 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1116 ,  H01L27/112 ,  H01L27/11286 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11568

摘要： A semiconductor memory device including a memory cell array, a first row decoder adjacent the memory cell array, and a second row decoder adjacent the memory cell array. A memory cell array may include first and second memory cell blocks on respective first and second semiconductor layers. The first memory cell block may include a first word line coupled to a first row of memory cells on the first semiconductor layer, the second memory cell block may include a second word line coupled to a second row of memory cells on the second semiconductor layer, and the first word line may be between the first and second semiconductor layers. The first row decoder may be configured to control the first word line, and the second row decoder may be configured to control the second word line. A first wiring may electrically connect the first row decoder and the first word line, and a second wiring may electrically connect the second row decoder and the second word line.

摘要翻译： 一种半导体存储器件，包括存储单元阵列，与存储单元阵列相邻的第一行解码器以及与存储单元阵列相邻的第二行解码器。 存储单元阵列可以包括在相应的第一和第二半导体层上的第一和第二存储单元块。 第一存储单元块可以包括耦合到第一半导体层上的第一行存储单元的第一字线，第二存储单元块可以包括耦合到第二半导体层上的第二行存储单元的第二字线， 并且第一字线可以在第一和第二半导体层之间。 第一行解码器可以被配置为控制第一字线，并且第二行解码器可以被配置为控制第二字线。 第一布线可以电连接第一行解码器和第一字线，并且第二布线可电连接第二行解码器和第二字线。

公开(公告)号：US08048727B2

公开(公告)日：2011-11-01

申请号：US12687545

申请日：2010-01-14

申请人： Jae-Hoon Jang ,  Soon-Moon Jung ,  Young-Seop Rah ,  Han-Byung Park

发明人： Jae-Hoon Jang ,  Soon-Moon Jung ,  Young-Seop Rah ,  Han-Byung Park

IPC分类号： H01L21/00

CPC分类号： H01L27/11 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/1116

摘要： An SRAM device includes a substrate having at least one cell active region in a cell array region and a plurality of peripheral active regions in a peripheral circuit region, a plurality of stacked cell gate patterns in the cell array region, and a plurality of peripheral gate patterns disposed on the peripheral active regions in the peripheral circuit region. Metal silicide layers are disposed on at least one portion of the peripheral gate patterns and on the semiconductor substrate near the peripheral gate patterns, and buried layer patterns are disposed on the peripheral gate patterns and on at least a portion of the metal silicide layers and the portions of the semiconductor substrate near the peripheral gate patterns. An etch stop layer and a protective interlayer-insulating layer are disposed around the peripheral gate patterns and on the cell array region. Methods of forming an SRAM device are also disclosed.

摘要翻译： SRAM器件包括：在单元阵列区域中具有至少一个单元有源区和外围电路区中的多个外围有源区，单元阵列区中的多个堆叠单元栅极图案和多个外围栅极的基板 设置在外围电路区域的外围有源区上的图案。 金属硅化物层设置在外围栅极图案的至少一部分上以及半导体衬底附近的外围栅极图案上，并且掩埋层图案设置在外围栅极图案和金属硅化物层的至少一部分上，并且 半导体衬底在周边栅极图案附近的部分。 蚀刻停止层和保护性层间绝缘层设置在周围栅极图案和电池阵列区域周围。 还公开了形成SRAM器件的方法。

公开(公告)号：US20100120217A1

公开(公告)日：2010-05-13

申请号：US12687545

申请日：2010-01-14

申请人： Jae-Hoon Jang ,  Soon-Moon Jung ,  Young-Seop Rah ,  Han-Byung Park

发明人： Jae-Hoon Jang ,  Soon-Moon Jung ,  Young-Seop Rah ,  Han-Byung Park

IPC分类号： H01L21/762

CPC分类号： H01L27/11 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/1116

摘要： An SRAM device includes a substrate having at least one cell active region in a cell array region and a plurality of peripheral active regions in a peripheral circuit region, a plurality of stacked cell gate patterns in the cell array region, and a plurality of peripheral gate patterns disposed on the peripheral active regions in the peripheral circuit region. Metal silicide layers are disposed on at least one portion of the peripheral gate patterns and on the semiconductor substrate near the peripheral gate patterns, and buried layer patterns are disposed on the peripheral gate patterns and on at least a portion of the metal silicide layers and the portions of the semiconductor substrate near the peripheral gate patterns. An etch stop layer and a protective interlayer-insulating layer are disposed around the peripheral gate patterns and on the cell array region. Methods of forming an SRAM device are also disclosed.

摘要翻译： SRAM器件包括：在单元阵列区域中具有至少一个单元有源区和外围电路区中的多个外围有源区，单元阵列区中的多个堆叠单元栅极图案和多个外围栅极的基板 设置在外围电路区域的外围有源区上的图案。 金属硅化物层设置在外围栅极图案的至少一部分上以及半导体衬底附近的外围栅极图案上，并且掩埋层图案设置在外围栅极图案和金属硅化物层的至少一部分上，并且 半导体衬底在周边栅极图案附近的部分。 蚀刻停止层和保护性层间绝缘层设置在周围栅极图案和电池阵列区域周围。 还公开了形成SRAM器件的方法。

公开(公告)号：US07671389B2

公开(公告)日：2010-03-02

申请号：US11385473

申请日：2006-03-21

申请人： Jae-Hoon Jang ,  Soon-Moon Jung ,  Young-Seop Rah ,  Han-Byung Park

发明人： Jae-Hoon Jang ,  Soon-Moon Jung ,  Young-Seop Rah ,  Han-Byung Park

IPC分类号： H01L31/112

CPC分类号： H01L27/11 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/1116

摘要： An SRAM device includes a substrate having at least one cell active region in a cell array region and a plurality of peripheral active regions in a peripheral circuit region, a plurality of stacked cell gate patterns in the cell array region, and a plurality of peripheral gate patterns disposed on the peripheral active regions in the peripheral circuit region. Metal silicide layers are disposed on at least one portion of the peripheral gate patterns and on the semiconductor substrate near the peripheral gate patterns, and buried layer patterns are disposed on the peripheral gate patterns and on at least a portion of the metal silicide layers and the portions of the semiconductor substrate near the peripheral gate patterns. An etch stop layer and a protective interlayer-insulating layer are disposed around the peripheral gate patterns and on the cell array region. Methods of forming an SRAM device are also disclosed.

摘要翻译： SRAM器件包括：在单元阵列区域中具有至少一个单元有源区和外围电路区中的多个外围有源区，单元阵列区中的多个堆叠单元栅极图案和多个外围栅极的基板 设置在外围电路区域的外围有源区上的图案。 金属硅化物层设置在外围栅极图案的至少一部分上以及半导体衬底附近的外围栅极图案上，并且掩埋层图案设置在外围栅极图案和金属硅化物层的至少一部分上，并且 半导体衬底在周边栅极图案附近的部分。 蚀刻停止层和保护性层间绝缘层设置在周围栅极图案和电池阵列区域周围。 还公开了形成SRAM器件的方法。

公开(公告)号：US20060216886A1

公开(公告)日：2006-09-28

申请号：US11385473

申请日：2006-03-21

申请人： Jae-Hoon Jang ,  Soon-Moon Jung ,  Young-Seop Rah ,  Han-Byung Park

发明人： Jae-Hoon Jang ,  Soon-Moon Jung ,  Young-Seop Rah ,  Han-Byung Park

IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L29/94 ,  H01L29/76 ,  H01L31/119

CPC分类号： H01L27/11 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/1116

摘要： An SRAM device includes a substrate having at least one cell active region in a cell array region and a plurality of peripheral active regions in a peripheral circuit region, a plurality of stacked cell gate patterns in the cell array region, and a plurality of peripheral gate patterns disposed on the peripheral active regions in the peripheral circuit region. Metal silicide layers are disposed on at least one portion of the peripheral gate patterns and on the semiconductor substrate near the peripheral gate patterns, and buried layer patterns are disposed on the peripheral gate patterns and on at least a portion of the metal silicide layers and the portions of the semiconductor substrate near the peripheral gate patterns. An etch stop layer and a protective interlayer-insulating layer are disposed around the peripheral gate patterns and on the cell array region. Methods of forming an SRAM device are also disclosed.

摘要翻译： SRAM器件包括：在单元阵列区域中具有至少一个单元有源区和外围电路区中的多个外围有源区，单元阵列区中的多个堆叠单元栅极图案和多个外围栅极的基板 设置在外围电路区域的外围有源区上的图案。 金属硅化物层设置在外围栅极图案的至少一部分上以及半导体衬底附近的外围栅极图案上，并且掩埋层图案设置在外围栅极图案和金属硅化物层的至少一部分上，并且 半导体衬底在周边栅极图案附近的部分。 蚀刻停止层和保护性层间绝缘层设置在周围栅极图案和电池阵列区域周围。 还公开了形成SRAM器件的方法。

公开(公告)号：US07589375B2

公开(公告)日：2009-09-15

申请号：US11642297

申请日：2006-12-20

申请人： Jae-Hoon Jang ,  Soon-Moon Jung ,  Jong-Hyuk Kim ,  Young-Seop Rah ,  Han-Byung Park

发明人： Jae-Hoon Jang ,  Soon-Moon Jung ,  Jong-Hyuk Kim ,  Young-Seop Rah ,  Han-Byung Park

IPC分类号： H01L27/115

CPC分类号： H01L27/11 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/1116

摘要： A non-volatile memory device includes a semiconductor substrate including a cell array region and a peripheral circuit region. A first cell unit is on the semiconductor substrate in the cell array region, and a cell insulating layer is on the first cell unit. A first active body layer is in the cell insulating layer and over the first cell unit, and a second cell unit is on the first active body layer. The device further includes a peripheral transistor on the semiconductor substrate in the peripheral circuit region. The peripheral transistor has a gate pattern and source/drain regions, and a metal silicide layer is on the gate pattern and/or on the source/drain regions of the peripheral transistor. A peripheral insulating layer is on the metal silicide layer and the peripheral transistor, and an etching protection layer is between the cell insulating layer and the peripheral insulating layer and between the metal silicide layer and the peripheral insulating layer.

摘要翻译： 非易失性存储器件包括包括单元阵列区域和外围电路区域的半导体衬底。 第一单元单元位于单元阵列区域中的半导体基板上，单元绝缘层位于第一单元单元上。 第一有源体层位于单元绝缘层中并在第一单元单元上，第二单元单元位于第一活性体层上。 该器件还包括在外围电路区域中的半导体衬底上的外围晶体管。 外围晶体管具有栅极图案和源极/漏极区域，并且金属硅化物层位于外围晶体管的栅极图案和/或源极/漏极区域上。 外围绝缘层位于金属硅化物层和外围晶体管上，蚀刻保护层位于电池绝缘层和外围绝缘层之间以及金属硅化物层和外围绝缘层之间。

公开(公告)号：US20070096197A1

公开(公告)日：2007-05-03

申请号：US11642297

申请日：2006-12-20

申请人： Jae-Hoon Jang ,  Soon-Moon Jung ,  Jong-Hyuk Kim ,  Young-Seop Rah ,  Han-Byung Park

发明人： Jae-Hoon Jang ,  Soon-Moon Jung ,  Jong-Hyuk Kim ,  Young-Seop Rah ,  Han-Byung Park

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L27/11 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/1116

摘要： A non-volatile memory device includes a semiconductor substrate including a cell array region and a peripheral circuit region. A first cell unit is on the semiconductor substrate in the cell array region, and a cell insulating layer is on the first cell unit. A first active body layer is in the cell insulating layer and over the first cell unit, and a second cell unit is on the first active body layer. The device further includes a peripheral transistor on the semiconductor substrate in the peripheral circuit region. The peripheral transistor has a gate pattern and source/drain regions, and a metal silicide layer is on the gate pattern and/or on the source/drain regions of the peripheral transistor. A peripheral insulating layer is on the metal silicide layer and the peripheral transistor, and an etching protection layer is between the cell insulating layer and the peripheral insulating layer and between the metal silicide layer and the peripheral insulating layer.

摘要翻译： 非易失性存储器件包括包括单元阵列区域和外围电路区域的半导体衬底。 第一单元单元位于单元阵列区域中的半导体基板上，单元绝缘层位于第一单元单元上。 第一有源体层位于单元绝缘层中并在第一单元单元上，第二单元单元位于第一活性体层上。 该器件还包括在外围电路区域中的半导体衬底上的外围晶体管。 外围晶体管具有栅极图案和源极/漏极区域，并且金属硅化物层位于外围晶体管的栅极图案和/或源极/漏极区域上。 外围绝缘层位于金属硅化物层和外围晶体管上，蚀刻保护层位于电池绝缘层和外围绝缘层之间以及金属硅化物层和外围绝缘层之间。

公开(公告)号：US07602028B2

公开(公告)日：2009-10-13

申请号：US11653890

申请日：2007-01-17

申请人： Yang-Soo Son ,  Young-Seop Rah ,  Won-Seok Cho ,  Soon-Moon Jung ,  Jae-Hoon Jang ,  Young-Chul Jang

发明人： Yang-Soo Son ,  Young-Seop Rah ,  Won-Seok Cho ,  Soon-Moon Jung ,  Jae-Hoon Jang ,  Young-Chul Jang

IPC分类号： H01L29/76

CPC分类号： H01L27/115 ,  H01L21/76895 ,  H01L21/8221 ,  H01L23/481 ,  H01L23/485 ,  H01L27/0688 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11551 ,  H01L2924/0002 ,  H01L2924/00

摘要： A NAND flash memory device includes a lower semiconductor layer and an upper semiconductor layer located over the lower semiconductor layer, a first drain region and a first source region located in the lower semiconductor layer, and a second drain region and a second source region located in the upper semiconductor layer. A first gate structure is located on the lower semiconductor layer, and a second gate structure is located on the upper semiconductor layer. A bit line is located over the upper semiconductor layer, and at least one bit line plug is connected between the bit line and the first drain region, where the at least one bit line plug extends through a drain throughhole located in the upper semiconductor layer.

摘要翻译： NAND闪速存储器件包括下半导体层和位于下半导体层上的上半导体层，位于下半导体层中的第一漏区和第一源区，以及位于下半导体层中的第二漏区和第二源区 上半导体层。 第一栅极结构位于下半导体层上，第二栅极结构位于上半导体层上。 位线位于上半导体层上方，并且至少一位位线插头连接在位线和第一漏极区之间，其中至少一位位线插头延伸穿过位于上半导体层中的漏极通孔。

公开(公告)号：US20080087932A1

公开(公告)日：2008-04-17

申请号：US11653890

申请日：2007-01-17

申请人： Yang-Soo Son ,  Young-Seop Rah ,  Won-Seok Cho ,  Soon-Moon Jung ,  Jae-Hoon Jang ,  Young-Chul Jang

发明人： Yang-Soo Son ,  Young-Seop Rah ,  Won-Seok Cho ,  Soon-Moon Jung ,  Jae-Hoon Jang ,  Young-Chul Jang

IPC分类号： H01L29/788

CPC分类号： H01L27/115 ,  H01L21/76895 ,  H01L21/8221 ,  H01L23/481 ,  H01L23/485 ,  H01L27/0688 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11551 ,  H01L2924/0002 ,  H01L2924/00

摘要： A NAND flash memory device includes a lower semiconductor layer and an upper semiconductor layer located over the lower semiconductor layer, a first drain region and a first source region located in the lower semiconductor layer, and a second drain region and a second source region located in the upper semiconductor layer. A first gate structure is located on the lower semiconductor layer, and a second gate structure is located on the upper semiconductor layer. A bit line is located over the upper semiconductor layer, and at least one bit line plug is connected between the bit line and the first drain region, where the at least one bit line plug extends through a drain throughhole located in the upper semiconductor layer.

摘要翻译： NAND闪速存储器件包括下半导体层和位于下半导体层上的上半导体层，位于下半导体层中的第一漏区和第一源区，以及位于下半导体层中的第二漏区和第二源区 上半导体层。 第一栅极结构位于下半导体层上，第二栅极结构位于上半导体层上。 位线位于上半导体层上方，并且至少一位位线插头连接在位线和第一漏极区之间，其中至少一位位线插头延伸穿过位于上半导体层中的漏极通孔。