公开(公告)号：US20140097465A1

公开(公告)日：2014-04-10

申请号：US13646799

申请日：2012-10-08

申请人： Mayank Shrivastava ,  Harald Gossner

发明人： Mayank Shrivastava ,  Harald Gossner

IPC分类号： H01L29/74 ,  H01L21/332

CPC分类号： H01L27/0817 ,  H01L21/845 ,  H01L27/1211

摘要： Some aspects relate to a semiconductor device disposed on a semiconductor substrate. The device includes an STI region that laterally surrounds a base portion of a semiconductor fin. An anode region, which has a first conductivity type, and a cathode region, which has a second conductivity type, are arranged in an upper portion of the semiconductor fin. A first doped base region, which has the second conductivity type, is arranged in the base of the fin underneath the anode region. A second doped base region, which has the first conductivity type, is arranged in the base of the fin underneath the cathode region. A current control unit is arranged between the anode region and the cathode region. The current control unit is arranged to selectively enable and disable current flow in the upper portion of the fin based on a trigger signal. Other devices and methods are also disclosed.

摘要翻译： 一些方面涉及设置在半导体衬底上的半导体器件。 该器件包括横向围绕半导体鳍片的基底部分的STI区域。 具有第一导电类型的阳极区域和具有第二导电类型的阴极区域布置在半导体鳍片的上部。 具有第二导电类型的第一掺杂基极区布置在阳极区域下方的翅片的底部。 具有第一导电类型的第二掺杂基区布置在阴极区下方的鳍的底部。 电流控制单元设置在阳极区域和阴极区域之间。 电流控制单元被布置为基于触发信号来选择性地启用和禁止鳍的上部中的电流。 还公开了其它装置和方法。

公开(公告)号：US08643090B2

公开(公告)日：2014-02-04

申请号：US12408839

申请日：2009-03-23

申请人： Mayank Shrivastava ,  Harald Gossner ,  Ramgopal Rao ,  Maryam Shojaei Baghini

发明人： Mayank Shrivastava ,  Harald Gossner ,  Ramgopal Rao ,  Maryam Shojaei Baghini

IPC分类号： H01L29/66

CPC分类号： H01L29/0653 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66659 ,  H01L29/7835

摘要： In various embodiments, a semiconductor device is provided. The semiconductor device may include a first source/drain region, a second source/drain region, an active region electrically coupled between the first source/drain region and the second source/drain region, a trench disposed between the second source/drain region and at least a portion of the active region, a first isolation layer disposed over the bottom and the sidewalls of the trench, electrically conductive material disposed over the isolation layer in the trench, a second isolation layer disposed over the active region, and a gate region disposed over the second isolation layer. The electrically conductive material may be coupled to an electrical contact.

摘要翻译： 在各种实施例中，提供半导体器件。 半导体器件可以包括第一源极/漏极区域，第二源极/漏极区域，电耦合在第一源极/漏极区域和第二源极/漏极区域之间的有源区域，设置在第二源极/漏极区域和第二源极/ 所述有源区的至少一部分，设置在所述沟槽的底部和所述侧壁上的第一隔离层，设置在所述沟槽中的所述隔离层上的导电材料，设置在所述有源区上的第二隔离层和栅极区 设置在第二隔离层上。 导电材料可以耦合到电接触。

公开(公告)号：US20130250461A1

公开(公告)日：2013-09-26

申请号：US13429577

申请日：2012-03-26

申请人： Mayank Shrivastava ,  Christian Russ ,  Harald Gossner

发明人： Mayank Shrivastava ,  Christian Russ ,  Harald Gossner

IPC分类号： H02H9/04

CPC分类号： H02H9/046

摘要： Some embodiments relate to an electrostatic discharge (ESD) protection device to protect a circuit from an ESD event. The ESD protection device includes first and second trigger elements. Upon detecting an ESD pulse, the first trigger element provides a first trigger signal having a first pulse length. The second trigger element, upon detecting the ESD pulse, provides a second trigger signal having a second pulse length. The second pulse length is different from the first pulse length. A primary shunt shunts power of the ESD pulse away from the ESD susceptible circuit based on the first trigger signal. A current control element selectively pumps current due to the ESD pulse into a substrate of the primary shunt based on the second trigger signal.

摘要翻译： 一些实施例涉及用于保护电路免受ESD事件的静电放电（ESD）保护装置。 ESD保护装置包括第一和第二触发元件。 在检测到ESD脉冲时，第一触发元件提供具有第一脉冲长度的第一触发信号。 第二触发元件在检测到ESD脉冲时提供具有第二脉冲长度的第二触发信号。 第二脉冲长度与第一脉冲长度不同。 基于第一触发信号，主分流器将ESD脉冲的功率分配离开ESD敏感电路。 电流控制元件基于第二触发信号选择性地将由于ESD脉冲引起的电流泵送到主分流器的衬底中。

公开(公告)号：US08536648B2

公开(公告)日：2013-09-17

申请号：US13020368

申请日：2011-02-03

申请人： Mayank Shrivastava ,  Cornelius Christian Russ ,  Harald Gossner ,  Ramgopal Rao

发明人： Mayank Shrivastava ,  Cornelius Christian Russ ,  Harald Gossner ,  Ramgopal Rao

IPC分类号： H01L29/76

CPC分类号： H01L29/1095 ,  H01L21/26513 ,  H01L27/088 ,  H01L29/0634 ,  H01L29/0642 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/0873 ,  H01L29/0878 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/267 ,  H01L29/41775 ,  H01L29/45 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66575 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7816 ,  H01L29/7835 ,  H01L29/7842

摘要： In an embodiment of the invention, a semiconductor device includes a first region having a first doping type, a channel region having the first doping type disposed in the first region, and a retrograde well having a second doping type. The second doping type is opposite to the first doping type. The retrograde well has a shallower layer with a first peak doping and a deeper layer with a second peak doping higher than the first peak doping. The device further includes a drain region having the second doping type over the retrograde well. An extended drain region is disposed in the retrograde well, and couples the channel region with the drain region. An isolation region is disposed between a gate overlap region of the extended drain region and the drain region. A length of the drain region is greater than a depth of the isolation region.

公开(公告)号：US08390970B2

公开(公告)日：2013-03-05

申请号：US12912781

申请日：2010-10-27

申请人： Harald Gossner ,  David Johnsson ,  Wolfgang Soldner

发明人： Harald Gossner ,  David Johnsson ,  Wolfgang Soldner

IPC分类号： H02H9/00

CPC分类号： H02H9/046

摘要： A method and a system for ESD protection are provided. In one embodiment, the system comprises a circuit comprising at least one non-linear element, an application module configured to apply a set of current pulses to the circuit, a determination module configured to determine at least one frequency-dependent and amplitude-dependent transfer function of the circuit based on the set of applied current pulses, a modeling module configured to model at least one frequency-dependent and current-dependent impedance of the at least one non-linear element, and a simulation module to simulate a transmission to the circuit based on the model.

摘要翻译： 提供了ESD保护的方法和系统。 在一个实施例中，系统包括包括至少一个非线性元件的电路，被配置为将一组电流脉冲施加到电路的应用模块，被配置为确定至少一个频率相关和幅度相关的转移 基于所施加的电流脉冲集合的电路的功能，被配置为对所述至少一个非线性元件的至少一个频率相关和依赖于电流的阻抗建模的建模模块，以及模拟模块，用于模拟到 电路基于模型。

公开(公告)号：US08093689B2

公开(公告)日：2012-01-10

申请号：US11772272

申请日：2007-07-02

申请人： Wolfgang Stadler ,  Harald Gossner ,  Reinhold Gaertner

发明人： Wolfgang Stadler ,  Harald Gossner ,  Reinhold Gaertner

IPC分类号： H01L23/58

CPC分类号： H01L23/60 ,  H01L2223/6677 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00

摘要： A semiconductor sensor device is electrically coupled to an object. An attachment member attaches the semiconductor sensor device to the object. The attachment member comprises a first conductive contact region and a second conductive contact region. An insulating portion is electrically isolates the semiconductor sensor device from the first conductive contact region and second conductive contact region.

摘要翻译： 半导体传感器装置电耦合到物体。 附接构件将半导体传感器装置附接到物体。 附接构件包括第一导电接触区域和第二导电接触区域。 绝缘部分将半导体传感器装置与第一导电接触区域和第二导电接触区域电隔离。

公开(公告)号：US07919816B2

公开(公告)日：2011-04-05

申请号：US11506683

申请日：2006-08-18

申请人： Harald Gossner ,  Christian Russ

发明人： Harald Gossner ,  Christian Russ

IPC分类号： H01L23/62

CPC分类号： H01L27/1211 ,  H01L27/0288 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/8086 ,  H01L2029/7857

摘要： A gate controlled fin resistance element for use as an electrostatic discharge (ESD) protection element in an electrical circuit has a fin structure having a first connection region, a second connection region and a channel region formed between the first and second connection regions. Furthermore, the fin resistance element has a gate region formed at least over a part of the surface of the channel region. The gate region is electrically coupled to a gate control device, which gate control device controls an electrical potential applied to the gate region in such a way that the gate controlled fin resistance element has a high electrical resistance during a first operating state of the electrical circuit and a lower electrical resistance during a second operating state, which is characterized by the occurrence of an ESD event.

摘要翻译： 在电路中用作静电放电（ESD）保护元件的栅极控制鳍电阻元件具有鳍状结构，其具有形成在第一和第二连接区域之间的第一连接区域，第二连接区域和沟道区域。 此外，散热片电阻元件具有形成在通道区域的表面的至少一部分上的栅极区域。 栅极区域电耦合到栅极控制装置，栅极控制装置控制施加到栅极区域的电位，使得栅极控制的鳍状电阻元件在电路的第一操作状态期间具有高电阻 并且在第二操作状态期间具有较低的电阻，其特征在于发生ESD事件。

公开(公告)号：US07838948B2

公开(公告)日：2010-11-23

申请号：US11668916

申请日：2007-01-30

申请人： Harald Gossner

发明人： Harald Gossner

IPC分类号： H01L27/112

CPC分类号： H01L29/41758 ,  H01L29/41791 ,  H01L29/4238 ,  H01L29/7831 ,  H01L29/785

摘要： In an embodiment, an apparatus includes a first field effect transistor including a first source contact region, a first drain contact region and a first plurality of fins overlying a substrate, a first gate overlying the first plurality of fins, the first source contact region coupled to first ends of the first plurality of fins, and a second field effect transistor including a second source contact region, a second drain contact region, and a second plurality of fins overlying the substrate, a second gate overlying the second plurality of fins, and an interconnection contact region overlying the substrate, electrically coupling the first drain contact region and the second source contact region and abutting the first and the second pluralities of fins.

摘要翻译： 在一个实施例中，装置包括第一场效应晶体管，其包括第一源极接触区域，第一漏极接触区域和覆盖衬底的第一多个鳍片，覆盖第一多个鳍片的第一栅极，第一源极接触区域耦合 到第一多个散热片的第一端，以及第二场效应晶体管，包括第二源极接触区域，第二漏极接触区域和覆盖在衬底上的第二多个鳍片，覆盖第二多个鳍片的第二栅极，以及 覆盖所述衬底的互连接触区域，电耦合所述第一漏极接触区域和所述第二源极接触区域并且邻接所述第一和第二多个鳍片。

公开(公告)号：US20100200916A1

公开(公告)日：2010-08-12

申请号：US12369821

申请日：2009-02-12

申请人： Harald Gossner ,  Ramgopal Rao ,  Angada Sachid ,  Ashish Pal ,  Ram Asra

发明人： Harald Gossner ,  Ramgopal Rao ,  Angada Sachid ,  Ashish Pal ,  Ram Asra

IPC分类号： H01L29/78

CPC分类号： H01L29/165 ,  H01L21/26586 ,  H01L29/0657 ,  H01L29/083 ,  H01L29/0834 ,  H01L29/66356 ,  H01L29/7391

摘要： In an embodiment, a semiconductor device is provided. The semiconductor device may include a substrate having a main processing surface, a first source/drain region comprising a first material of a first conductivity type, a second source/drain region comprising a second material of a second conductivity type, wherein the second conductivity type is different from the first conductivity type, a body region electrically coupled between the first source/drain region and the second source/drain region, wherein the body region extends deeper into the substrate than the first source/drain region in a first direction that is perpendicular to the main processing surface of the substrate, a gate dielectric disposed over the body region, and a gate region disposed over the gate dielectric, wherein the gate region overlaps with at least a part of the first source/drain region and with a part of the body region in the first direction.

摘要翻译： 在一个实施例中，提供了半导体器件。 半导体器件可以包括具有主处理表面的衬底，包括第一导电类型的第一材料的第一源极/漏极区域，包括第二导电类型的第二材料的第二源极/漏极区域，其中第二导电类型 不同于第一导电类型，电耦合在第一源极/漏极区域和第二源极/漏极区域之间的主体区域，其中主体区域在第一方向上比第一源极/漏极区域在第一方向 垂直于基板的主处理表面，设置在主体区域上的栅极电介质和设置在栅极电介质上的栅极区域，其中栅极区域与第一源极/漏极区域的至少一部分重叠， 的身体区域在第一个方向。

公开(公告)号：US07694247B2

公开(公告)日：2010-04-06

申请号：US10569986

申请日：2005-03-17

申请人： Kai Esmark ,  Harald Gossner ,  Wolfgang Stadler ,  Marin Streibl

发明人： Kai Esmark ,  Harald Gossner ,  Wolfgang Stadler ,  Marin Streibl

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： A program-controlled arrangement for the identification of ESD and/or latch-up weak points in the design or in the concept of an integrated circuit comprises a pre-processor, which processes first data about the description of the integrated circuit, second data about already ESD-characterized circuit parts of the integrated circuit, and third data which contain information about ESD test standards. A simulator device is connected downstream of the pre-processor which has a simulator which, by using the fourth and fifth data generated by the pre-processor, performs an ESD simulation of the integrated circuit, which has a monitoring controller for controlling the ESD simulation sequence in the simulator. An analysis device is connected downstream of the simulator device, which performs an evaluation of the sixth data generated in the simulator device with regard to their physical validity and meaningfulness, and marks the simulation runs having physically relevant ESD failure events.

摘要翻译： 用于在设计中或集成电路的概念中识别ESD和/或闭锁弱点的程序控制布置包括预处理器，其处理关于集成电路的描述的第一数据，关于 集成电路已经具有ESD特征的电路部件，以及包含有关ESD测试标准信息的第三个数据。 模拟器装置连接在预处理器的下游，其具有模拟器，通过使用由预处理器生成的第四和第五数据执行集成电路的ESD模拟，其具有用于控制ESD模拟的监视控制器 序列在模拟器中。 分析装置连接在模拟器装置的下游，对其模拟装置的物理有效性和有意义性进行评估，并对具有物理上相关的ESD故障事件的模拟运行进行标记。