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1.发明授权Integrating the formation of I/O and core MOS devices with MOS capacitors and resistors 有权将I / O和核心MOS器件的形成与MOS电容器和电阻器集成公开(公告)号：US08294216B2
公开(公告)日：2012-10-23
申请号：US12191817
申请日：2008-08-14
IPC分类号： H01L27/11
CPC分类号： H01L27/0629 , H01L27/105 , H01L27/11 , H01L27/1116 , H01L28/20 , H01L28/40 , H01L29/94
摘要： An integrated circuit structure includes a semiconductor substrate, and a first and a second MOS device. The first MOS device includes a first gate dielectric over the semiconductor substrate, wherein the first gate dielectric is planar; and a first gate electrode over the first gate dielectric. The second MOS device includes a second gate dielectric over the semiconductor substrate; and a second gate electrode over the second gate dielectric. The second gate electrode has a height greater than a height of the first gate electrode. The second gate dielectric includes a planar portion underlying the second gate electrode, and sidewall portions extending on sidewalls of the second gate electrode.
摘要翻译： 集成电路结构包括半导体衬底和第一和第二MOS器件。 第一MOS器件包括半导体衬底上的第一栅极电介质，其中第一栅极电介质是平面的; 以及位于第一栅极电介质上的第一栅电极。 第二MOS器件包括半导体衬底上的第二栅极电介质; 以及在所述第二栅极电介质上方的第二栅电极。 第二栅电极的高度大于第一栅电极的高度。 第二栅极电介质包括在第二栅电极下面的平面部分和在第二栅电极的侧壁上延伸的侧壁部分。
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2.发明申请Integrating the Formation of I/O and Core MOS Devices with MOS Capacitors and Resistors 有权将I / O和核心MOS器件的形成与MOS电容器和电阻器集成公开(公告)号：US20100038692A1
公开(公告)日：2010-02-18
申请号：US12191817
申请日：2008-08-14
IPC分类号： H01L27/11
CPC分类号： H01L27/0629 , H01L27/105 , H01L27/11 , H01L27/1116 , H01L28/20 , H01L28/40 , H01L29/94
摘要： An integrated circuit structure includes a semiconductor substrate, and a first and a second MOS device. The first MOS device includes a first gate dielectric over the semiconductor substrate, wherein the first gate dielectric is planar; and a first gate electrode over the first gate dielectric. The second MOS device includes a second gate dielectric over the semiconductor substrate; and a second gate electrode over the second gate dielectric. The second gate electrode has a height greater than a height of the first gate electrode. The second gate dielectric includes a planar portion underlying the second gate electrode, and sidewall portions extending on sidewalls of the second gate electrode.
摘要翻译： 集成电路结构包括半导体衬底和第一和第二MOS器件。 第一MOS器件包括半导体衬底上的第一栅极电介质，其中第一栅极电介质是平面的; 以及位于第一栅极电介质上的第一栅电极。 第二MOS器件包括半导体衬底上的第二栅极电介质; 以及在所述第二栅极电介质上方的第二栅电极。 第二栅电极的高度大于第一栅电极的高度。 第二栅极电介质包括在第二栅电极下面的平面部分和在第二栅电极的侧壁上延伸的侧壁部分。
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公开(公告)号：US07898037B2
公开(公告)日：2011-03-01
申请号：US11833128
申请日：2007-08-02
申请人： Harry Chuang , Kong-Beng Thei , Mong Song Liang , Jung-Hui Kao , Sheng-Chen Chung , Chung Long Cheng , Shun-Jang Liao
发明人： Harry Chuang , Kong-Beng Thei , Mong Song Liang , Jung-Hui Kao , Sheng-Chen Chung , Chung Long Cheng , Shun-Jang Liao
IPC分类号： H01L29/78
CPC分类号： H01L29/785 , H01L21/76807 , H01L21/76895 , H01L21/76897 , H01L21/823431 , H01L21/823437 , H01L21/823475 , H01L29/41791 , H01L29/66795 , H01L2029/7858
摘要： A semiconductor structure and methods of forming the same are provided. The semiconductor structure includes a semiconductor substrate; a first inter-layer dielectric (ILD) over the semiconductor substrate; a contact extending from a top surface of the first ILD into the first ILD; a second ILD over the first ILD; a bottom inter-metal dielectric (IMD) over the second ILD; and a dual damascene structure comprising a metal line in the IMD and a via in the second ILD, wherein the via is connected to the contact.
摘要翻译： 提供半导体结构及其形成方法。 半导体结构包括半导体衬底; 半导体衬底上的第一层间电介质（ILD）; 从第一ILD的顶表面延伸到第一ILD中的接触; 第一个ILD的第二个ILD; 在第二ILD上的底部金属间电介质（IMD）; 以及包括IMD中的金属线和第二ILD中的通孔的双镶嵌结构，其中所述通孔连接到所述触点。
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公开(公告)号：US07868361B2
公开(公告)日：2011-01-11
申请号：US11766425
申请日：2007-06-21
IPC分类号： H01L21/76
CPC分类号： H01L29/66477 , H01L21/823412 , H01L21/823418 , H01L21/823462 , H01L27/0629 , H01L27/088 , H01L27/0922 , H01L29/7848
摘要： A semiconductor device having a core device with a high-k gate dielectric and an I/O device with a silicon dioxide or other non-high-k gate dielectric, and a method of fabricating such a device. A core well and an I/O well are created in a semiconductor substrate and separated by an isolation structure. An I/O device is formed over the I/O well and has a silicon dioxide or a low-k gate dielectric. A resistor may be formed on an isolation structure adjacent to the core well. A core-well device such as a transistor is formed over the core well, and has a high-k gate dielectric. In some embodiments, a p-type I/O well and an n-type I/O well are created. In a preferred embodiment, the I/O device or devices are formed prior to forming the core device and protected with a sacrificial layer until the core device is fabricated.
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公开(公告)号：US08349732B2
公开(公告)日：2013-01-08
申请号：US12176133
申请日：2008-07-18
申请人： Harry Chuang , Hung-Chih Tsai , Keh-Chiang Ku , Kong-Beng Thei , Mong Song Liang
发明人： Harry Chuang , Hung-Chih Tsai , Keh-Chiang Ku , Kong-Beng Thei , Mong Song Liang
CPC分类号： H01L29/4983 , H01L21/28518 , H01L21/28525 , H01L29/165 , H01L29/6656 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： A device and a method for forming a metal silicide is presented. A device, which includes a gate region, a source region, and a drain region, is formed on a substrate. A metal is disposed on the substrate, followed by a first anneal, forming a metal silicide on at least one of the gate region, the source region, and the drain region. The unreacted metal is removed from the substrate. The metal silicide is implanted with atoms. The implant is followed by a super anneal of the substrate.
摘要翻译： 提出了一种用于形成金属硅化物的器件和方法。 在基板上形成包括栅极区域，源极区域和漏极区域的器件。 在基板上设置金属，接着进行第一退火，在栅极区域，源极区域和漏极区域中的至少一个上形成金属硅化物。 将未反应的金属从基材上除去。 金属硅化物被注入原子。 植入物之后是衬底的超退火。
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公开(公告)号：US08286114B2
公开(公告)日：2012-10-09
申请号：US11833119
申请日：2007-08-02
申请人： Harry Chuang , Kong-Beng Thei , Mong Song Liang , Sheng-Chen Chung , Chih-Tsung Yao , Jung-Hui Kao , Chung Long Cheng , Gary Shen , Gwan Sin Chang
发明人： Harry Chuang , Kong-Beng Thei , Mong Song Liang , Sheng-Chen Chung , Chih-Tsung Yao , Jung-Hui Kao , Chung Long Cheng , Gary Shen , Gwan Sin Chang
IPC分类号： G06F17/50
CPC分类号： H01L29/785 , H01L21/76807 , H01L21/76895 , H01L21/76897 , H01L21/823431 , H01L21/823437 , H01L21/823475 , H01L29/41791 , H01L29/66795 , H01L2029/7858
摘要： A method for defining a layout of 3-D devices, such as a finFET, is provided. The method includes determining an area required by a desired 3-D device and designing a circuit using planar devices having an equivalent area. The planar device corresponding to the desired 3-D device is used to layout a circuit design, thereby allowing circuit and layout designers to work at a higher level without the need to specify each individual fin or 3-D structure. Thereafter, the planar design may be converted to a 3-D design by replacing planar active areas with 3-D devices occupying an equivalent area.
摘要翻译： 提供了一种用于定义诸如finFET的3-D器件的布局的方法。 该方法包括确定期望的3-D设备所需的区域和使用具有等效面积的平面设备来设计电路。 对应于期望的3-D器件的平面器件用于布局电路设计，从而允许电路和布局设计者在更高级别工作，而不需要指定每个单独的鳍或3-D结构。 此后，平面设计可以通过用占据等同面积的3-D器件代替平面有源区域而被转换成3维设计。
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7.发明申请Semiconductor Device with both I/O and Core Components and Method of Fabricating Same 有权具有I / O和核心组件的半导体器件及其制造方法公开(公告)号：US20110076813A1
公开(公告)日：2011-03-31
申请号：US12961167
申请日：2010-12-06
IPC分类号： H01L21/8238
CPC分类号： H01L29/66477 , H01L21/823412 , H01L21/823418 , H01L21/823462 , H01L27/0629 , H01L27/088 , H01L27/0922 , H01L29/7848
摘要： A semiconductor device having a core device with a high-k gate dielectric and an I/O device with a silicon dioxide or other non-high-k gate dielectric, and a method of fabricating such a device. A core well and an I/O well are created in a semiconductor substrate and separated by an isolation structure. An I/O device is formed over the I/O well and has a silicon dioxide or a low-k gate dielectric. A resistor may be formed on an isolation structure adjacent to the core well. A core-well device such as a transistor is formed over the core well, and has a high-k gate dielectric. In some embodiments, a p-type I/O well and an n-type I/O well are created. In a preferred embodiment, the I/O device or devices are formed prior to forming the core device and protected with a sacrificial layer until the core device is fabricated.
摘要翻译： 具有具有高k栅极电介质的核心器件和具有二氧化硅或其它非高k栅极电介质的I / O器件的半导体器件及其制造方法。 核心阱和I / O阱在半导体衬底中产生并被隔离结构隔开。 I / O器件形成在I / O阱上，并具有二氧化硅或低k栅极电介质。 可以在与芯井相邻的隔离结构上形成电阻器。 在核心阱上形成诸如晶体管的核心阱器件，并且具有高k栅极电介质。 在一些实施例中，产生p型I / O阱和n型I / O阱。 在优选实施例中，在形成核心器件之前形成I / O器件或器件，并用牺牲层进行保护，直到制造核心器件。
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公开(公告)号：US08237201B2
公开(公告)日：2012-08-07
申请号：US11807654
申请日：2007-05-30
申请人： Harry Chuang , Kong-Beng Thei , Jen-Bin Hsu , Chung Long Cheng , Mong Song Liang
发明人： Harry Chuang , Kong-Beng Thei , Jen-Bin Hsu , Chung Long Cheng , Mong Song Liang
IPC分类号： H01L27/118
CPC分类号： H01L27/0207 , H01L27/11 , H01L27/1104
摘要： A semiconductor structure includes an array of unit metal-oxide-semiconductor (MOS) devices arranged in a plurality of rows and a plurality of columns is provided. Each of the unit MOS devices includes an active region laid out in a row direction and a gate electrode laid out in a column direction. The semiconductor structure further includes a first unit MOS device in the array and a second unit MOS device in the array, wherein active regions of the first and the second unit MOS devices have different conductivity types.
摘要翻译： 半导体结构包括以多行排列的单位金属氧化物半导体（MOS）器件的阵列，并且提供多个列。 每个单位MOS器件包括布置在行方向上的有源区和沿列方向布置的栅电极。 半导体结构还包括阵列中的第一单元MOS器件和阵列中的第二单元MOS器件，其中第一和第二单位MOS器件的有源区具有不同的导电类型。
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9.发明授权公开(公告)号：US08558278B2
公开(公告)日：2013-10-15
申请号：US11849798
申请日：2007-09-04
申请人： Harry Chuang , Kong-Beng Thei , Wen-Huei Guo , Mong Song Liang
发明人： Harry Chuang , Kong-Beng Thei , Wen-Huei Guo , Mong Song Liang
IPC分类号： H01L27/092
CPC分类号： H01L21/823807 , H01L29/7843
摘要： A strain-induced layer is formed atop a MOS device in order to increase carrier mobility in the channel region. The dimension of the strain-induced layer in preferred embodiments may lead to an optimized drive current increase and improved drive current uniformity in an NMOS and PMOS device. An advantage of the preferred embodiments is that improved device performance is obtained without adding complex processing steps. A further advantage of the preferred embodiments is that the added processing steps can be readily integrated into a known CMOS process flow. Moreover, the creation of the photo masks defining the tensile and compressive strain-induced layers does not require extra design work on an existed design database.
摘要翻译： 应变感应层形成在MOS器件的顶部，以增加沟道区中的载流子迁移率。 在优选实施例中，应变诱导层的尺寸可导致优化的驱动电流增加和改进的NMOS和PMOS器件中的驱动电流均匀性。 优选实施例的优点是在不添加复杂的处理步骤的情况下获得改进的设备性能。 优选实施例的另一个优点是附加的处理步骤可以容易地集成到已知的CMOS工艺流程中。 此外，创建定义拉伸和压缩应变诱导层的光罩不需要对现有设计数据库进行额外的设计工作。
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公开(公告)号：US20120286368A1
公开(公告)日：2012-11-15
申请号：US13558109
申请日：2012-07-25
申请人： Harry Chuang , Kong-Beng Thei , Jen-Bin Hsu , Chung Long Cheng , Mong Song Liang
发明人： Harry Chuang , Kong-Beng Thei , Jen-Bin Hsu , Chung Long Cheng , Mong Song Liang
IPC分类号： H01L27/088
CPC分类号： H01L27/0207 , H01L27/11 , H01L27/1104
摘要： A semiconductor structure includes an array of unit metal-oxide-semiconductor (MOS) devices arranged in a plurality of rows and a plurality of columns is provided. Each of the unit MOS devices includes an active region laid out in a row direction and a gate electrode laid out in a column direction. The semiconductor structure further includes a first unit MOS device in the array and a second unit MOS device in the array, wherein active regions of the first and the second unit MOS devices have different conductivity types.
摘要翻译： 半导体结构包括以多行排列的单位金属氧化物半导体（MOS）器件的阵列，并且提供多个列。 每个单位MOS器件包括布置在行方向上的有源区和沿列方向布置的栅电极。 半导体结构还包括阵列中的第一单元MOS器件和阵列中的第二单元MOS器件，其中第一和第二单位MOS器件的有源区具有不同的导电类型。
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