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    Multi-step chemical vapor deposition method for thin film transistors
    4.
    发明授权
    Multi-step chemical vapor deposition method for thin film transistors 失效
    薄膜晶体管的多步骤化学气相沉积方法

    公开(公告)号：US5567476A

    公开(公告)日：1996-10-22

    申请号：US427772

    申请日：1995-04-25

    申请人： Kam S. Law ,  Robert Robertson ,  Michael Kollrack ,  Angela T. Lee ,  Takako Takehara ,  Guofu J. Feng ,  Dan Maydan

    发明人： Kam S. Law ,  Robert Robertson ,  Michael Kollrack ,  Angela T. Lee ,  Takako Takehara ,  Guofu J. Feng ,  Dan Maydan

    IPC分类号： H01L21/205 ,  C23C16/24 ,  C23C16/34 ,  H01L21/31 ,  H01L21/318 ,  H01L21/336 ,  H01L29/786 ,  C23C16/00

    CPC分类号： H01L29/66765 ,  C23C16/24 ,  C23C16/345

    摘要： A multi-step CVD method for thin film transistor is disclosed. The method can be carried out by depositing a high quality g-SiN.sub.x at a low deposition rate on top of an average quality gate nitride deposited at a high deposition rate and then depositing an amorphous silicon layer. It also applies in a process where high quality amorphous silicon is first deposited at a low deposition rate on a gate nitride layer to form an interface, and then average quality amorphous silicon is deposited at a high deposition rate to complete the silicon layer. The unique process can be applied whenever an interface exists with an active semiconductor layer of amorphous silicon. The process is applicable to either the back channel etched TFT device or the etch stopped TFT device.

    摘要翻译： 公开了薄膜晶体管的多步CVD方法。 该方法可以通过在以高沉积速率沉积的平均质量的氮化镓的顶部上以低沉积速率沉积高质量的g-SiNx，然后沉积非晶硅层来进行。 它也适用于首先在栅极氮化物层上以低沉积速率沉积高品质非晶硅以形成界面的过程，然后以高沉积速率淀积平均质量的非晶硅以完成硅层。 每当与非晶硅的有源半导体层存在界面时，可以应用独特的工艺。 该工艺适用于后沟道蚀刻TFT器件或蚀刻停止的TFT器件。

    Multi-step chemical vapor deposition method for thin film transistors
    5.
    发明授权
    Multi-step chemical vapor deposition method for thin film transistors 失效
    薄膜晶体管的多步骤化学气相沉积方法

    公开(公告)号：US5441768A

    公开(公告)日：1995-08-15

    申请号：US193310

    申请日：1994-02-08

    申请人： Kam S. Law ,  Robert Robertson ,  Michael Kollrack ,  Angela T. Lee ,  Takako Takehara ,  Guofu J. Feng ,  Dan Maydan

    发明人： Kam S. Law ,  Robert Robertson ,  Michael Kollrack ,  Angela T. Lee ,  Takako Takehara ,  Guofu J. Feng ,  Dan Maydan

    IPC分类号： H01L21/205 ,  C23C16/24 ,  C23C16/34 ,  H01L21/31 ,  H01L21/318 ,  H01L21/336 ,  H01L29/786 ,  C23C16/22

    CPC分类号： H01L29/66765 ,  C23C16/24 ,  C23C16/345

    摘要： An improved method of depositing films of a gate silicon nitride and an amorphous silicon on a thin film transistor substrate at high deposition rates while maintaining superior film quality is provided. The material near the interface between the amorphous silicon and the nitride are deposited at a low deposition rate which produces superior quality films. The region away from the interface are deposited at a high deposition rate which produces lesser, but still good quality films. By using this method, superior quality thin film transistors can be produced at very high efficiency. The method can be carried out by depositing a high quality g-SiN.sub.x at a low deposition rate on top of an average quality gate nitride deposited at a high deposition rate and then depositing an amorphous silicon layer. It also applies in a process where high quality amorphous silicon is first deposited at a low deposition rate on a gate nitride layer to form an interface, and then average quality amorphous silicon is deposited at a high deposition rate to complete the silicon layer. The unique process can be applied whenever an interface exists with an active semiconductor layer of amorphous silicon. The process is applicable to either the back channel etched TFT device or the etch stopped TFT device.

    摘要翻译： 提供了一种在保持优异的膜质量的同时以高沉积速率在薄膜晶体管基板上沉积栅极氮化硅和非晶硅的膜的改进方法。 在非晶硅和氮化物之间的界面附近的材料以低沉积速率沉积，其产生优质的膜。 离开界面的区域以高沉积速率沉积，其产生较小但仍然是优质的膜。 通过使用该方法，能够以非常高的效率制造出优质的薄膜晶体管。 该方法可以通过在以高沉积速率沉积的平均质量的氮化镓的顶部上以低沉积速率沉积高质量的g-SiNx，然后沉积非晶硅层来进行。 它也适用于首先在栅极氮化物层上以低沉积速率沉积高品质非晶硅以形成界面的过程，然后以高沉积速率淀积平均质量的非晶硅以完成硅层。 每当与非晶硅的有源半导体层存在界面时，可以应用独特的工艺。 该工艺适用于后沟道蚀刻TFT器件或蚀刻停止的TFT器件。

    Annealing an amorphous film using microwave energy
    6.
    发明授权
    Annealing an amorphous film using microwave energy 失效
    使用微波能量退火非晶膜

    公开(公告)号：US06172322B2

    公开(公告)日：2001-01-09

    申请号：US08965939

    申请日：1997-11-07

    申请人： Quanyuan Shang ,  Robert McCormick Robertson ,  Kam S. Law ,  Takako Takehara ,  Taekyung Won ,  Sheng Sun

    发明人： Quanyuan Shang ,  Robert McCormick Robertson ,  Kam S. Law ,  Takako Takehara ,  Taekyung Won ,  Sheng Sun

    IPC分类号： H05B680

    CPC分类号： C23C16/56

    摘要： A system and method for annealing a film on a substrate in a processing chamber, including a microwave generator disposed to provide microwaves to an area within the interior of the chamber. The microwaves have a frequency such that the film is substantially absorptive at the frequency but the substrate is not substantially absorptive at the frequency. A waveguide distributes the microwaves over the surface of the film to provide a substantially uniform dosage of microwaves over the surface of the film. The method includes depositing a film on a substrate in the processing chamber. During at least a portion of the time of the depositing step, microwaves are generated having a frequency such that the film has an absorption peak at the frequency but the substrate lacks a substantial absorption peak at the frequency. The microwaves are directed towards the film.

    摘要翻译： 一种用于对处理室中的基板上的膜进行退火的系统和方法，该处理室包括微波发生器，微波发生器被设置成向腔室内部的区域提供微波。 微波的频率使得膜在频率上基本上是吸收性的，但是基底在频率上基本上不吸收。 波导将微波分布在膜的表面上，以在膜的表面上提供基本上均匀的微波用量的微波。 该方法包括在处理室中的衬底上沉积膜。 在沉积步骤的至少一部分时间内，产生具有频率使得该膜在频率处具有吸收峰但基底在该频率处缺少实质吸收峰的频率的微波。 微波指向电影。

    Low temperature process for TFT fabrication
    7.
    发明授权
    Low temperature process for TFT fabrication 有权
    TFT制造的低温工艺

    公开(公告)号：US07300829B2

    公开(公告)日：2007-11-27

    申请号：US10453333

    申请日：2003-06-02

    申请人： Mark Hsiao ,  Dong-Kil Yim ,  Takako Takehara ,  Quanyuan Shang ,  William R. Harshbarger ,  Woong-Kwon Kim ,  Duk-Chul Yun ,  Youn-Gyung Chang

    发明人： Mark Hsiao ,  Dong-Kil Yim ,  Takako Takehara ,  Quanyuan Shang ,  William R. Harshbarger ,  Woong-Kwon Kim ,  Duk-Chul Yun ,  Youn-Gyung Chang

    IPC分类号： H01L21/20 ,  H01L21/84 ,  H01L21/336

    CPC分类号： H01L29/66765 ,  H01L29/4908 ,  H01L29/78669 ,  H01L29/78678

    摘要： Method of fabricating a thin-film transistor (TFT) in which a gate metal is deposited onto a substrate in order to form the gate of the thin-film transistor. The substrate may be an insulative substrate or a color filter. In a first method, the gate metal is subjected to an H2 plasma. After subjecting the gate metal to an H2 plasma, the gate insulating film is deposited onto the gate. In a second method, first and second layers of gate insulating film are respectively deposited on the gate at a first and second deposition rates. One layer is deposited under H2 or argon dilution conditions and has improved insulating conditions while the other layer serves to lower the overall compressive stress of the dual layer gate insulator. In a third method, an n+ silicon film is formed on a substrate by maintaining a flow of silane, phosphine and hydrogen gas into a processing chamber at substrate temperatures of about 300° C. or less.

    摘要翻译： 制造薄膜晶体管（TFT）的方法，其中栅极金属沉积到衬底上以形成薄膜晶体管的栅极。 衬底可以是绝缘衬底或滤色器。 在第一种方法中，栅极金属经受H 2 H 2等离子体。 在栅极金属经受H 2等离子体后，栅极绝缘膜沉积在栅极上。 在第二种方法中，第一和第二栅极绝缘膜层分别以第一和第二沉积速率沉积在栅极上。 一层沉积在H 2 N 2或氩稀释条件下，并且具有改善的绝缘条件，而另一层用于降低双层栅极绝缘体的整体压应力。 在第三种方法中，通过在约300℃或更低的衬底温度下保持硅烷，膦和氢气流入处理室，在衬底上形成n + +硅膜。

    Method of reducing an electrostatic charge on a substrate during a PECVD process
    8.
    发明授权
    Method of reducing an electrostatic charge on a substrate during a PECVD process 失效
    在PECVD工艺期间减少衬底上的静电电荷的方法

    公开(公告)号：US06827987B2

    公开(公告)日：2004-12-07

    申请号：US09927698

    申请日：2001-07-27

    申请人： Tae Kyung Won ,  Soo Young Choi ,  Takako Takehara ,  William R. Harshbarger

    发明人： Tae Kyung Won ,  Soo Young Choi ,  Takako Takehara ,  William R. Harshbarger

    IPC分类号： H05H124

    CPC分类号： C23C16/4581

    摘要： Provided herein is a method of reducing an electrostatic charge on a substrate during a plasma enhanced chemical vapor deposition process, comprising the step of depositing a conductive layer onto a top surface of a susceptor support plate disposed within a deposition chamber wherein the conductive layer dissipates the electrostatic charge on the bottom surface of the substrate during a plasma enhanced chemical vapor deposition process. Also provided are a method of depositing a thin film during a plasma enhanced chemical vapor deposition process using the methods disclosed herein and a conductive susceptor.

    摘要翻译： 本文提供的是一种在等离子体增强化学气相沉积工艺期间减少衬底上的静电电荷的方法，其包括将导电层沉积到设置在沉积室内的基座支撑板的顶表面上的步骤，其中导电层消散 在等离子体增强化学气相沉积工艺期间，在衬底的底表面上的静电荷。 还提供了使用本文公开的方法和导电基座在等离子体增强化学气相沉积工艺期间沉积薄膜的方法。

    Method of depositing amorphous silicon based films having controlled conductivity
    9.
    发明授权
    Method of depositing amorphous silicon based films having controlled conductivity 失效
    沉积具有受控导电性的非晶硅基膜的方法

    公开(公告)号：US06352910B1

    公开(公告)日：2002-03-05

    申请号：US09249041

    申请日：1999-02-12

    申请人： William R. Harshbarger ,  Takako Takehara ,  Jeff C. Olsen ,  Regina Qiu ,  Yvonne LeGrice ,  Guofu J. Feng ,  Robert M. Robertson ,  Kam Law

    发明人： William R. Harshbarger ,  Takako Takehara ,  Jeff C. Olsen ,  Regina Qiu ,  Yvonne LeGrice ,  Guofu J. Feng ,  Robert M. Robertson ,  Kam Law

    IPC分类号： H01L2120

    CPC分类号： C23C16/24

    摘要： Deposition methods for preparing amorphous silicon based films with controlled resistivity and low stress are described. Such films can be used as the interlayer in FED manufacturing. They can also be used in other electronic devices which require films with controlled resistivity in the range between those of an insulator and of a conductor. The deposition methods described in the present invention employ the method of chemical vapor deposition or plasma-enhanced chemical vapor deposition; other film deposition techniques, such as physical vapor deposition, also may be used. In one embodiment, an amorphous silicon-based film is formed by introducing into a deposition chamber a silicon-based volatile, a conductivity-increasing volatile including one or more components for increasing the conductivity of the amorphous silicon-based film, and a conductivity-decreasing volatile including one or more components for decreasing the conductivity of the amorphous silicon-based film.

    摘要翻译： 描述了制备具有受控电阻率和低应力的非晶硅基膜的沉积方法。 这种膜可用作FED制造中的中间层。 它们也可用于需要具有在绝缘体和导体之间的范围内的受控电阻率的膜的其它电子器件。 本发明中描述的沉积方法采用化学气相沉积或等离子体增强化学气相沉积的方法; 也可以使用其它成膜技术，例如物理气相沉积。 在一个实施方案中，通过向沉积室中引入硅基挥发物，包含一种或多种用于增加非晶硅基膜的导电性的组分的增加电导率的挥发性，并且导电性 - 降低挥发性，包括一种或多种用于降低非晶硅基膜的导电性的组分。

    Low temperature process for TFT fabrication
    10.
    发明授权
    Low temperature process for TFT fabrication 有权
    TFT制造的低温工艺

    公开(公告)号：US07915114B2

    公开(公告)日：2011-03-29

    申请号：US11946040

    申请日：2007-11-27

    申请人： Mark Hsiao ,  Dong-Kil Yim ,  Takako Takehara ,  Quanyuan Shang ,  William R. Harshbarger ,  Woong-Kwon Kim ,  Duk-Chul Yun ,  Youn-Gyung Chang

    发明人： Mark Hsiao ,  Dong-Kil Yim ,  Takako Takehara ,  Quanyuan Shang ,  William R. Harshbarger ,  Woong-Kwon Kim ,  Duk-Chul Yun ,  Youn-Gyung Chang

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/66765 ,  H01L29/4908 ,  H01L29/78669 ,  H01L29/78678

    摘要： Method of fabricating a thin-film transistor (TFT) in which a gate metal is deposited onto a substrate in order to form the gate of the thin-film transistor. The substrate may be an insulative substrate or a color filter. In a first method, the gate metal is subjected to an H2 plasma. After subjecting the gate metal to an H2 plasma, the gate insulating film is deposited onto the gate. In a second method, first and second layers of gate insulating film are respectively deposited on the gate at a first and second deposition rates. One layer is deposited under H2 or argon dilution conditions and has improved insulating conditions while the other layer serves to lower the overall compressive stress of the dual layer gate insulator. In a third method, an n+ silicon film is formed on a substrate by maintaining a flow of silane, phosphine and hydrogen gas into a processing chamber at substrate temperatures of about 300° C. or less.

    摘要翻译： 制造薄膜晶体管（TFT）的方法，其中栅极金属沉积到衬底上以形成薄膜晶体管的栅极。 衬底可以是绝缘衬底或滤色器。 在第一种方法中，栅极金属经受H 2等离子体。 在使栅极金属进入H 2等离子体之后，栅极绝缘膜沉积在栅极上。 在第二种方法中，第一和第二栅极绝缘膜层分别以第一和第二沉积速率沉积在栅极上。 在H2或氩稀释条件下沉积一层，并且具有改善的绝缘条件，而另一层用于降低双层栅极绝缘体的总体压应力。 在第三种方法中，通过在约300℃或更低的衬底温度下将硅烷，膦和氢气流入处理室，在衬底上形成n +硅膜。