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    Method of IGZO and ZNO TFT fabrication with PECVD SiO2 passivation
    1.
    发明授权
    Method of IGZO and ZNO TFT fabrication with PECVD SiO2 passivation 有权
    使用PECVD SiO2钝化的IGZO和ZNO TFT制造方法

    公开(公告)号：US09553195B2

    公开(公告)日：2017-01-24

    申请号：US13490813

    申请日：2012-06-07

    Applicant: Jrjyan Jerry Chen ,  Soo Young Choi ,  Dong-Kil Yim ,  Yan Ye

    Inventor： Jrjyan Jerry Chen ,  Soo Young Choi ,  Dong-Kil Yim ,  Yan Ye

    IPC: H01L21/336 ,  H01L29/786 ,  H01L29/66

    CPC classification number: H01L29/66969 ,  H01L21/02565 ,  H01L29/78606 ,  H01L29/7869

    Abstract: The present invention generally relates to a method of manufacturing a TFT. The TFT has an active channel that comprises IGZO or zinc oxide. After the source and drain electrodes are formed, but before the passivation layers or etch stop layers are deposited thereover, the active channel is exposed to an N2O or O2 plasma. The interface between the active channel and the passivation layers or etch stop layers are either altered or damaged during formation of the source and drain electrodes. The N2O or O2 plasma alters and repairs the interface between the active channel and the passivation or etch stop layers.

    Abstract translation: 本发明一般涉及制造TFT的方法。 TFT具有包含IGZO或氧化锌的有源沟道。 在形成源电极和漏电极之后，但是在钝化层或蚀刻停止层之前沉积，活性通道暴露于N 2 O或O 2等离子体。 活性通道与钝化层或蚀刻停止层之间的界面在形成源极和漏极期间被改变或损坏。 N2O或O2等离子体改变和修复有源通道与钝化或蚀刻停止层之间的界面。

    Low temperature process for TFT fabrication
    5.
    发明授权
    Low temperature process for TFT fabrication 有权
    TFT制造的低温工艺

    公开(公告)号：US07915114B2

    公开(公告)日：2011-03-29

    申请号：US11946040

    申请日：2007-11-27

    Applicant: Mark Hsiao ,  Dong-Kil Yim ,  Takako Takehara ,  Quanyuan Shang ,  William R. Harshbarger ,  Woong-Kwon Kim ,  Duk-Chul Yun ,  Youn-Gyung Chang

    Inventor： Mark Hsiao ,  Dong-Kil Yim ,  Takako Takehara ,  Quanyuan Shang ,  William R. Harshbarger ,  Woong-Kwon Kim ,  Duk-Chul Yun ,  Youn-Gyung Chang

    IPC: H01L21/8238

    CPC classification number: H01L29/66765 ,  H01L29/4908 ,  H01L29/78669 ,  H01L29/78678

    Abstract: Method of fabricating a thin-film transistor (TFT) in which a gate metal is deposited onto a substrate in order to form the gate of the thin-film transistor. The substrate may be an insulative substrate or a color filter. In a first method, the gate metal is subjected to an H2 plasma. After subjecting the gate metal to an H2 plasma, the gate insulating film is deposited onto the gate. In a second method, first and second layers of gate insulating film are respectively deposited on the gate at a first and second deposition rates. One layer is deposited under H2 or argon dilution conditions and has improved insulating conditions while the other layer serves to lower the overall compressive stress of the dual layer gate insulator. In a third method, an n+ silicon film is formed on a substrate by maintaining a flow of silane, phosphine and hydrogen gas into a processing chamber at substrate temperatures of about 300° C. or less.

    Abstract translation: 制造薄膜晶体管（TFT）的方法，其中栅极金属沉积到衬底上以形成薄膜晶体管的栅极。 衬底可以是绝缘衬底或滤色器。 在第一种方法中，栅极金属经受H 2等离子体。 在使栅极金属进入H 2等离子体之后，栅极绝缘膜沉积在栅极上。 在第二种方法中，第一和第二栅极绝缘膜层分别以第一和第二沉积速率沉积在栅极上。 在H2或氩稀释条件下沉积一层，并且具有改善的绝缘条件，而另一层用于降低双层栅极绝缘体的总体压应力。 在第三种方法中，通过在约300℃或更低的衬底温度下将硅烷，膦和氢气流入处理室，在衬底上形成n +硅膜。

    Microcrystalline silicon thin film transistor
    6.
    发明授权
    Microcrystalline silicon thin film transistor 失效
    微晶硅薄膜晶体管

    公开(公告)号：US07833885B2

    公开(公告)日：2010-11-16

    申请号：US12323872

    申请日：2008-11-26

    Applicant: Tae Kyung Won ,  Soo Young Choi ,  Dong Kil Yim ,  Jriyan Jerry Chen ,  Beom Soo Park

    Inventor： Tae Kyung Won ,  Soo Young Choi ,  Dong Kil Yim ,  Jriyan Jerry Chen ,  Beom Soo Park

    IPC: H01L21/00

    CPC classification number: H01L29/04 ,  C23C16/26 ,  H01J37/32009 ,  H01J37/32357 ,  H01J37/32862 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/0262 ,  H01L29/66742 ,  H01L29/7866

    Abstract: Methods for forming a microcrystalline silicon layer in a thin film transistor structure are provided. In one embodiment, a method for forming a microcrystalline silicon layer includes providing a substrate in a processing chamber, supplying a gas mixture having a hydrogen-based gas, a silicon-based gas and an argon gas into the processing chamber, the gas mixture having a volumetric flow ratio of the hydrogen-based gas to the silicon-based gas greater than about 100:1, wherein a volumetric flow ratio of the argon gas to the total combined flow of hydrogen-based gas and the silicon-based gas is between about 5 percent and about 40 percent, and maintaining a process pressure of the gas mixture within the processing chamber at greater than about 3 Torr while depositing a microcrystalline silicon layer on the substrate.

    Abstract translation: 提供了在薄膜晶体管结构中形成微晶硅层的方法。 在一个实施例中，一种形成微晶硅层的方法包括在处理室中提供衬底，将具有氢基气体，硅基气体和氩气的气体混合物供应到处理室中，所述气体混合物具有 氢基气体与硅基气体的体积流量比大于约100:1，其中氩气与氢气体和硅基气体的总合并流量的体积流量比在 约5％和约40％，并且在处理室内的气体混合物的工艺压力保持在大于约3Torr，同时在衬底上沉积微晶硅层。

    SUBSTRATE LIFT PIN SENSOR
    7.
    发明申请
    SUBSTRATE LIFT PIN SENSOR 审中-公开
    基板提升引脚传感器

    公开(公告)号：US20100013626A1

    公开(公告)日：2010-01-21

    申请号：US12501763

    申请日：2009-07-13

    Applicant: Chung-Hee Park ,  John M. White ,  Dong Kil Yim

    Inventor： Chung-Hee Park ,  John M. White ,  Dong Kil Yim

    IPC: G08B19/00 ,  B05C11/00

    CPC classification number: C23C16/4583 ,  C23C16/52 ,  H01L21/67259 ,  H01L21/68742

    Abstract: Embodiments disclosed herein include a method and apparatus for supporting a substrate. When a substrate is inserted into a processing chamber by an end effector robot, the substrate is placed on one or more lift pins. The lift pins may include a sensing mechanism that can detect whether the substrate is cracked, the lift pin is broken, or the lift pin sticks to the bushing. By detecting the aforementioned conditions, uniform, repeatable deposition may be obtained for multiple substrates.

    Abstract translation: 本文公开的实施例包括用于支撑衬底的方法和装置。 当通过端部执行器机器人将基板插入处理室时，将基板放置在一个或多个升降销上。 提升销可以包括感测机构，其可以检测基板是否破裂，提升销是否断裂，或者提升销是否粘附到套管上。 通过检测上述条件，可以获得对于多个基板的均匀的，可重复的沉积。

    MICROCRYSTALLINE SILICON THIN FILM TRANSISTOR
    8.
    发明申请
    MICROCRYSTALLINE SILICON THIN FILM TRANSISTOR 失效
    微晶硅薄膜晶体管

    公开(公告)号：US20090200552A1

    公开(公告)日：2009-08-13

    申请号：US12323872

    申请日：2008-11-26

    Applicant: Tae Kyung Won ,  Soo Young Choi ,  Dong Kil Yim ,  Jriyan Jerry Chen ,  Beom Soo Park

    Inventor： Tae Kyung Won ,  Soo Young Choi ,  Dong Kil Yim ,  Jriyan Jerry Chen ,  Beom Soo Park

    IPC: H01L29/04 ,  H01L21/20 ,  H01L21/00

    CPC classification number: H01L29/04 ,  C23C16/26 ,  H01J37/32009 ,  H01J37/32357 ,  H01J37/32862 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/0262 ,  H01L29/66742 ,  H01L29/7866

    Abstract: Methods for forming a microcrystalline silicon layer in a thin film transistor structure are provided. In one embodiment, a method for forming a microcrystalline silicon layer includes providing a substrate in a processing chamber, supplying a gas mixture having a hydrogen-based gas, a silicon-based gas and an argon gas into the processing chamber, the gas mixture having a volumetric flow ratio of the hydrogen-based gas to the silicon-based gas greater than about 100:1, wherein a volumetric flow ratio of the argon gas to the total combined flow of hydrogen-based gas and the silicon-based gas is between about 5 percent and about 40 percent, and maintaining a process pressure of the gas mixture within the processing chamber at greater than about 3 Torr while depositing a microcrystalline silicon layer on the substrate.

    Abstract translation: 提供了在薄膜晶体管结构中形成微晶硅层的方法。 在一个实施例中，一种形成微晶硅层的方法包括在处理室中提供衬底，将具有氢基气体，硅基气体和氩气的气体混合物供应到处理室中，所述气体混合物具有 氢基气体与硅基气体的体积流量比大于约100:1，其中氩气与氢气体和硅基气体的总合并流量的体积流量比在 约5％和约40％，并且在处理室内的气体混合物的工艺压力保持在大于约3Torr，同时在衬底上沉积微晶硅层。

    Reducing electrostatic charge by roughening the susceptor
    9.
    发明授权
    Reducing electrostatic charge by roughening the susceptor 有权
    通过粗化基座来减少静电电荷

    公开(公告)号：US08372205B2

    公开(公告)日：2013-02-12

    申请号：US11182168

    申请日：2005-07-15

    Applicant: Soo Young Choi ,  Beom Soo Park ,  Quanyuan Shang ,  John M. White ,  Dong-Kil Yim ,  Chung-Hee Park

    Inventor： Soo Young Choi ,  Beom Soo Park ,  Quanyuan Shang ,  John M. White ,  Dong-Kil Yim ,  Chung-Hee Park

    IPC: H01L21/306 ,  C23C16/00 ,  C23F1/00

    CPC classification number: C23C16/4581 ,  B24C1/06 ,  B24C1/10 ,  B24C3/322 ,  C23C16/4404 ,  C23C16/545 ,  C25D11/04 ,  C25D11/16 ,  C25D11/18 ,  H01J37/32082 ,  H01J37/32477 ,  H01J37/32559 ,  H01J37/32715 ,  H01L21/68757

    Abstract: A substrate support and method for fabricating the same are provided. In one embodiment of the invention, a substrate support includes an electrically conductive body having a substrate support surface that is covered by an electrically insulative coating. At least a portion of the coating centered on the substrate support surface has a surface finish of between about 200 to about 2000 micro-inches. In another embodiment, a substrate support includes an anodized aluminum body having a surface finish on the portion of the body adapted to support a substrate thereon of between about 200 to about 2000 micro-inches. In one embodiment, a substrate support assembly includes an electrically conductive body having a substrate support surface, a substrate support structure that is adapted to support the conductive body and the conductive body is covered by an electrically insulative coating.

    Abstract translation: 提供了一种基板支撑件及其制造方法。 在本发明的一个实施例中，衬底支撑件包括具有由电绝缘涂层覆盖的衬底支撑表面的导电体。 以基板支撑表面为中心的涂层的至少一部分具有介于约200至约2000微英寸之间的表面光洁度。 在另一个实施例中，衬底支撑件包括阳极化铝体，其在主体部分上具有表面光洁度，其适于在其上支撑约200至约2000微英寸的衬底。 在一个实施例中，衬底支撑组件包括具有衬底支撑表面的导电体，适于支撑导电体的衬底支撑结构，并且导电体被电绝缘涂层覆盖。

    Microcrystalline silicon thin film transistor
    10.
    发明授权
    Microcrystalline silicon thin film transistor 有权
    微晶硅薄膜晶体管

    公开(公告)号：US08076222B2

    公开(公告)日：2011-12-13

    申请号：US12204563

    申请日：2008-09-04

    Applicant: Tae Kyung Won ,  Soo Young Choi ,  Dong Kil Yim ,  Jriyan Jerry Chen ,  Beom Soo Park

    Inventor： Tae Kyung Won ,  Soo Young Choi ,  Dong Kil Yim ,  Jriyan Jerry Chen ,  Beom Soo Park

    IPC: H01L21/36

    CPC classification number: H01L21/0262 ,  C23C16/26 ,  H01L21/02532 ,  H01L21/02595 ,  H01L29/04 ,  H01L29/66765 ,  H01L29/78696

    Abstract: Methods for forming a microcrystalline silicon layer in a thin film transistor structure are provided. In one embodiment, a method for forming a microcrystalline silicon layer includes providing a substrate in a processing chamber, supplying a first gas mixture having a hydrogen containing gas to a silicon containing gas flow rate ratio greater than about 200:1 into the processing chamber, maintaining a first process pressure greater than about 6 Torr in the processing chamber to deposit a first microcrystalline silicon containing layer in presence of a plasma formed from the first gas mixture, supplying a second gas mixture into the processing chamber, and maintaining a second process pressure less than about 5 Torr in the processing chamber to deposit a second microcrystalline silicon containing layer in presence of a plasma formed from the second gas mixture.

    Abstract translation: 提供了在薄膜晶体管结构中形成微晶硅层的方法。 在一个实施例中，形成微晶硅层的方法包括在处理室中提供衬底，将具有含氢气体的第一气体混合物供给到大于约200:1的含硅气体流速比进入处理室， 在处理室中保持大于约6托的第一工艺压力，以在由第一气体混合物形成的等离子体存在下沉积第一微晶硅含量层，将第二气体混合物供应到处理室中，并保持第二工艺压力 在处理室中小于约5托，以在由第二气体混合物形成的等离子体存在下沉积第二微晶硅含量层。

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