公开(公告)号：US5628834A

公开(公告)日：1997-05-13

申请号：US438004

申请日：1995-05-09

Applicant: Matthew W. Copel ,  Rudolf M. Tromp

Inventor： Matthew W. Copel ,  Rudolf M. Tromp

IPC: C30B23/02 ,  C30B25/02 ,  C30B25/18 ,  H01L21/203 ,  H01L29/165

CPC classification number: C30B23/02 ,  C30B25/02 ,  C30B25/18 ,  C30B29/06 ,  C30B29/08 ,  C30B29/52 ,  Y10S148/072 ,  Y10S148/097

Abstract: The present invention broadly concerns layered structures of substantially-crystalline materials and processes for making such structures. More particularly, the invention concerns epitaxial growth of a substantially-crystalline layer of a first material on a substantially-crystalline second material different from the first material utilizing an approximately one monolayer thick monovalent surfactant element.

Abstract translation: 本发明广泛涉及基本结晶材料的层状结构和制造这种结构的方法。 更具体地，本发明涉及使用大约一个单层厚度的一价表面活性剂元件，在不同于第一材料的基本上为结晶的第二材料上的第一材料的基本晶体层的外延生长。

公开(公告)号：US5221367A

公开(公告)日：1993-06-22

申请号：US227955

申请日：1988-08-03

Applicant: Matthew F. Chisholm ,  Peter D. Kirchner ,  Alan C. Warren ,  Jerry M. Woodall

Inventor： Matthew F. Chisholm ,  Peter D. Kirchner ,  Alan C. Warren ,  Jerry M. Woodall

IPC: C30B25/02 ,  C30B29/40 ,  C30B29/68 ,  H01L21/20 ,  H01L21/203 ,  H01L29/201

CPC classification number: H01L21/02395 ,  H01L21/02463 ,  H01L21/02546 ,  Y10S148/072 ,  Y10S148/097 ,  Y10S438/933 ,  Y10S438/938

Abstract: Heterostructures having a large lattice mismatch between an upper epilayer and a substrate and a method of forming such structures having a thin intermediate layer are disclosed. The strain due to a lattice mismatch between the intermediate layer and the substrate is partially relieved by the formation of edge type dislocations which are localized and photoelectrically inactive. Growth of the intermediate layer is interrupted before it reaches the thickness at which the left over strain is relieved by 60 degree type threading dislocations. The upper epilayer is then grown in an unstrained and defect-free condition upon the intermediate layer where the unstrained lattice constant of the epilayer is about the same as the partially relieved strain lattice constant or the intermediate layer. An unstrained defect-free epilayer of InGaAs has been grown on a GaAs substrate with an intermediate layer 3-10 nm in thickness of InAs. Other large mismatch systems are disclosed, including, GaAs on Si with an intermediate layer of GaInAs.

公开(公告)号：US5164359A

公开(公告)日：1992-11-17

申请号：US511589

申请日：1990-04-20

Applicant: Joseph A. Calviello ,  Grayce A. Hickman

Inventor： Joseph A. Calviello ,  Grayce A. Hickman

IPC: H01L21/20 ,  H01L21/84

CPC classification number: H01L27/18 ,  H01L21/0237 ,  H01L21/0242 ,  H01L21/02433 ,  H01L21/02439 ,  H01L21/0245 ,  H01L21/02463 ,  H01L21/02488 ,  H01L21/02507 ,  H01L21/02546 ,  H01L21/02631 ,  H01L21/84 ,  Y10S148/025 ,  Y10S148/072 ,  Y10S148/097 ,  Y10S505/703 ,  Y10S505/704

Abstract: A semiconductor device and processing technique is provided for monolithic integration of a single crystal compound element semiconductor on a ceramic substrate. A high resistivity semi-insulating buffer layer is epitaxially grown on the ceramic substrate and has an elastically transitional lattice constant matching at its lower surface the lattice constant of the ceramic substrate, and matching at its upper surface the lattice constant of the semiconductor layer.

Abstract translation: 提供半导体器件和处理技术，用于将陶瓷衬底上的单晶复合元件半导体单片集成。 在陶瓷基板上外延生长高电阻半绝缘缓冲层，并且在其下表面具有弹性过渡晶格常数匹配陶瓷衬底的晶格常数，并在其上表面匹配半导体层的晶格常数。

公开(公告)号：US5108947A

公开(公告)日：1992-04-28

申请号：US470356

申请日：1990-01-25

Applicant: Piet M. Demeester ,  Ann M. Ackaert ,  Peter P. Van Daele ,  Dirk U. Lootens

Inventor： Piet M. Demeester ,  Ann M. Ackaert ,  Peter P. Van Daele ,  Dirk U. Lootens

IPC: H01L33/00 ,  H01L21/20 ,  H01L21/205 ,  H01L27/15

CPC classification number: H01L21/0262 ,  H01L21/02381 ,  H01L21/02546 ,  H01L21/02639 ,  Y10S148/026 ,  Y10S148/097 ,  Y10S438/945

Abstract: A method of growing a GaAs crystalline layer on a Si substrate by means of which mechanical stresses causing microcracks in the materials when cooled due to the difference in their thermal coefficients are reduced and the location of the microcrack is controlled to predetermined sites. Microcracks are deliberately induced in the GaAs layer at locations where the operation of the ultimate electronic device created on the material is not affected by applying to the substrate a SiO.sub.2 mask providing a deposition opening or window for the GaAs layer, which masks defines along the opening boundary at least one vertex in the cleavage direction of the GaAs crystals. The vertices in the mask create notches in the periphery of the deposited layer which determines the location of any microcracks.

公开(公告)号：US4962051A

公开(公告)日：1990-10-09

申请号：US272977

申请日：1988-11-18

Applicant: H. Ming Liaw

Inventor： H. Ming Liaw

IPC: H01L21/20 ,  H01L21/322 ,  H01L21/762

CPC classification number: H01L21/76243 ,  H01L21/3226 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  Y10S148/04 ,  Y10S148/059 ,  Y10S148/072 ,  Y10S148/097

Abstract: An improved method of fabricating a defect-free semiconductor layer and a semiconductor on insulator structure is provided by forming an isoelectronically doped semiconductor layer between a substrate and an semiconductor layer. The isoelectronic dopant atoms are different in atomic size than the atoms of the semiconductor material, thus misfit dislocations are created at the interface of the isoelectronically doped semiconductor layer due to lattice mismatch. Impurities and defects are not only gettered to the misfit dislocation sites, but are also prevented from propagating to the epitaxial layer. These misfit dislocations are thermally stable and are confined in a plane parallel to the interfaces of the isoelectronically doped semiconductor layer, thus very effective gettering agents. If the isoelectroncially doped semiconductor layer us also a heavily doped buried layer, no misfit dislocations are desired because the buried layer is an active device layer. In this case the isoelectronic dopant atoms may offset the non-isoelectronic dopant atoms in atomic size, thus no misfit dislocations are formed.

Abstract translation: 通过在衬底和半导体层之间形成等电子掺杂半导体层来提供制造无缺陷半导体层和绝缘体上半导体结构的改进方法。 等电子掺杂剂原子的原子尺寸与半导体材料的原子不同，因此由于晶格失配，在等电子掺杂半导体层的界面处产生失配位错。 杂质和缺陷不仅可以消除错配位错位点，而且可以防止传播到外延层。 这些失配位错是热稳定的，并且被限制在平行于等电子掺杂半导体层的界面的平面中，因此是非常有效的吸气剂。 如果等电子掺杂的半导体层也是重掺杂的掩埋层，则不需要失配位错，因为掩埋层是有源器件层。 在这种情况下，等电子掺杂剂原子可以以原子尺寸偏移非等电子掺杂原子，因此不会形成失配位错。

公开(公告)号：US4935385A

公开(公告)日：1990-06-19

申请号：US223036

申请日：1988-07-22

Applicant: David K. Biegelsen

Inventor： David K. Biegelsen

IPC: H01L21/20 ,  H01L21/36

CPC classification number: H01L21/02381 ,  H01L21/0237 ,  H01L21/02439 ,  H01L21/02469 ,  H01L21/02474 ,  H01L21/02477 ,  H01L21/02546 ,  Y10S117/913 ,  Y10S148/025 ,  Y10S148/097 ,  Y10S148/149 ,  Y10S148/154 ,  Y10S438/933

Abstract: Intermediate buffer films having a low plastic deformation threshold are provided for absorbing defects due to lattice mismatch and/or thermal coefficient of expansion mismatch between a substrate or layer support and an overlayer while concurrently providing a good template for subsequent crystalline growth at the overlayer. This is accomplished for diamond cubic structure substrates, such as Si or Ge or Si on sapphire or crystalline Si on glass, upon which are to be deposited lattice mismatch overlayers, such as, GaAs or ZnSe. Also, zinc blend type substrates, such as GaAs or InP may be employed with such intermediate buffer films. A characteristic of these intermediate buffer films is a substantially lower plastic deformation threshold compared to either the substrate support or the overlayer to be grown heteroepitaxially thereon. In particular, such high plastic deformable compound materials found suitable for such an intermediate buffer film are cubic III-V, II-VI or a I-VII zinc blend compound materials, respectively and specifically, (Zn.sub.X Cd.sub.Y Hg.sub.1-X-Y)(S.sub.A Se.sub.B Te.sub.1-A-B) and Cu(Cl.sub.X Br.sub.Y I.sub.1-X-Y) wherein X or Y respectively range between 0 and 1 such that X+ Y.ltoreq.1 and A and B respectively range between 0 and 1 such that A+B.ltoreq.1. Particular examples are GaAs, ZnSe, ZnS.sub.x Se.sub.1-x, CdS.sub.x Se.sub.1-x, HgS.sub.x Se.sub.1-x, CuCl, CuBr or CuI, et al.

Abstract translation: 提供具有低塑性变形阈值的中间缓冲膜用于吸收由于晶格失配和/或基底或层载体与覆盖层之间的膨胀失配的热系数而引起的缺陷，同时为覆盖层上随后的晶体生长同时提供良好的模板。 这对于金刚石立方结构衬底（例如蓝宝石上的Si或Ge或玻璃上的晶体Si），其上将沉积的晶格失配覆盖层（例如GaAs或ZnSe）而言是完成的。 此外，可以使用诸如GaAs或InP的锌共混型衬底与这种中间缓冲膜。 与衬底支撑体或异质外延生长的覆盖层相比，这些中间缓冲膜的特征是相当低的塑性变形阈值。 特别地，适用于这种中间缓冲膜的这种高塑性可变形化合物材料分别是立方体III-V，II-VI或I-VII锌混合物，分别具体地（ZnXCdYHg1-XY）（SASeBTe1-AB） 和Cu（ClXBrYI1-XY），其中X或Y分别在0和1之间变化，使得X + Y 1和A和B分别在0和1之间变化，使得A + B <1。 具体实例是GaAs，ZnSe，ZnSxSe1-x，CdSxSe1-x，HgSxSe1-x，CuCl，CuBr或CuI等。

公开(公告)号：US4935382A

公开(公告)日：1990-06-19

申请号：US265175

申请日：1988-10-31

Applicant: Wilbur D. Johnston, Jr. ,  Charles W. Tu

Inventor： Wilbur D. Johnston, Jr. ,  Charles W. Tu

IPC: H01L21/20 ,  H01L21/314 ,  H01L29/267

CPC classification number: H01L21/314 ,  H01L21/02387 ,  H01L21/02392 ,  H01L21/02488 ,  H01L21/02507 ,  H01L21/02543 ,  H01L21/02631 ,  H01L21/02661 ,  H01L29/267 ,  Y10S148/056 ,  Y10S148/072 ,  Y10S148/097 ,  Y10S438/957 ,  Y10S438/967

Abstract: A semiconductor epitaxial device structure is described in which there are alternate single crystal layers of semiconductor, insulator and semiconductor. A typical example is InP/CaF.sub.2 /InP. A process for producing such a structure is also described.

Abstract translation: 描述了半导体外延器件结构，其中存在半导体，绝缘体和半导体的交替单晶层。 一个典型的例子是InP / CaF2 / InP。 还描述了用于制造这种结构的方法。

公开(公告)号：US4866291A

公开(公告)日：1989-09-12

申请号：US211031

申请日：1988-06-24

Applicant: Tetsuya Shimada ,  Satoshi Itabashi ,  Katsunori Hatanaka

Inventor： Tetsuya Shimada ,  Satoshi Itabashi ,  Katsunori Hatanaka

IPC: H01L21/20 ,  H01L27/146 ,  H04N1/401

CPC classification number: H04N1/401 ,  H01L21/0242 ,  H01L21/02532 ,  H01L21/02557 ,  H01L21/0256 ,  H01L21/0262 ,  H01L21/02639 ,  H01L27/14665 ,  H01L27/14681 ,  Y10S148/014 ,  Y10S148/097 ,  Y10S148/152

Abstract: An image photosensor includes a photosensor unit a charge storage unit, and a switch unit, all of which are formed on a single-crystal semiconductor film grown from a single nucleus such that crystal formation is performed on a substrate having a free surface including a non-nucleus formation surface and a nucleus formation surface adjacent thereto. The non-nucleus formation surface has a low nucleation density. The nucleus formation surface has a sufficiently small area to allow growth of only the single nucleus and has a higher nucleation density than that of the non-nucleus formation surface.

公开(公告)号：US4581814A

公开(公告)日：1986-04-15

申请号：US681270

申请日：1984-12-13

Applicant: George K. Celler ,  Pradip K. Roy ,  Donald G. Schimmel ,  Lee E. Trimble

Inventor： George K. Celler ,  Pradip K. Roy ,  Donald G. Schimmel ,  Lee E. Trimble

IPC: H01L21/324 ,  H01L21/762 ,  H01L21/20 ,  H01L21/76

CPC classification number: H01L21/76297 ,  H01L21/324 ,  Y10S148/085 ,  Y10S148/086 ,  Y10S148/097 ,  Y10S148/122 ,  Y10S148/123 ,  Y10S438/928 ,  Y10S438/973 ,  Y10S438/977

Abstract: The efficacy of dielectrically isolated device formation on a substrate is substantially enhanced through a specific set of processing steps. In particular, before silicon oxide regions, e.g., gate oxide regions, are produced, bulk polycrystalline areas are heat treated to substantially increase their polycrystalline silicon grain size.

Abstract translation: 通过一组特定的处理步骤，显着地增强了在基片上的介电隔离器件形成的功效。 特别地，在制造氧化硅区域（例如栅极氧化物区域）之前，对大块多晶区域进行热处理以显着增加其多晶硅晶粒尺寸。

公开(公告)号：US4333989A

公开(公告)日：1982-06-08

申请号：US167757

申请日：1982-02-22

Applicant: Jun-Ichi Nishizawa ,  Kitsuhiro Kimura

Inventor： Jun-Ichi Nishizawa ,  Kitsuhiro Kimura

IPC: C30B25/18 ,  C23C16/44 ,  C30B19/12 ,  C30B29/20 ,  H01L21/20 ,  H01L21/205 ,  H01L21/86

CPC classification number: C30B19/12 ,  H01L21/02414 ,  H01L21/0242 ,  H01L21/02433 ,  H01L21/02532 ,  Y10S117/902 ,  Y10S148/072 ,  Y10S148/079 ,  Y10S148/097 ,  Y10S148/15

Abstract: A single crystal substrate for epitaxial growth thereon of a semiconductor layer. The substrate consisting essentially of sapphire (aluminum oxide) and at least one additive selected from a group consisting of oxides of gallium. A 87 mol percent content of gallium oxide is most preferred for a silicon layer. Similarly, an additive and its content should most preferably be selected depending on the semiconductor, which may be gallium phosphide, aluminium phosphide, or zinc sulphide.

Abstract translation: 用于在其上外延生长半导体层的单晶衬底。 该基底基本上由蓝宝石（氧化铝）和至少一种选自镓的氧化物的添加剂组成。 对于硅层来说，最优选87％的氧化镓含量。 类似地，添加剂及其含量最优选根据可以是磷化镓，磷化铝或硫化锌的半导体来选择。