公开(公告)号：US09181088B2

公开(公告)日：2015-11-10

申请号：US13218763

申请日：2011-08-26

申请人： Henri Sibuet ,  Xavier Baillin ,  Nicolas Sillon

发明人： Henri Sibuet ,  Xavier Baillin ,  Nicolas Sillon

IPC分类号： B32B15/01 ,  B81C3/00 ,  H01L23/10

CPC分类号： B81C3/001 ,  B81C2203/0109 ,  B81C2203/035 ,  H01L23/10 ,  H01L2224/8181 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/1461 ,  Y10T428/31678 ,  H01L2924/00

摘要： An assembly of two objects integral with each other through at least one linking element provided between both objects, said linking element including at least a first material portion comprising intermetallic compounds of a phase formed with a first brazing metal and a second metal the melting point of which is higher than that of the first brazing metal, said linking element further including at least a second material portion composed of at least a third metal, said second material portion contacting both objects.

摘要翻译： 两个物体的组合通过设置在两个物体之间的至少一个连接元件彼此成一体，所述连接元件至少包括第一材料部分，该第一材料部分包含与第一钎焊金属形成的相的金属间化合物和第二金属， 其高于第一钎焊金属，所述连接元件还包括至少由至少第三金属构成的第二材料部分，所述第二材料部分接触两个物体。

公开(公告)号：US08692385B2

公开(公告)日：2014-04-08

申请号：US13311146

申请日：2011-12-05

申请人： Aurélie Thuaire ,  Xavier Baillin ,  Nicolas Sillon

发明人： Aurélie Thuaire ,  Xavier Baillin ,  Nicolas Sillon

IPC分类号： H01L23/52 ,  B82Y10/00

CPC分类号： H01L21/76898

摘要： Device for connecting nano-objects to external electrical systems, and method for producing the device.According to the invention, which applies in particular to molecular characterization, a device including the following is produced: an upper layer equipped with upper contact pads to be connected to a nano-object; a lower layer, equipped with lower contact pads to be connected to an external electrical system; above the lower layer, a bonding layer including electrical through-vias in contact with the lower pads; and, between the bonding layer and the upper layer, at least two layers equipped with conductive lines and electrical vias, for connecting the upper pads to the lower pads.

摘要翻译： 用于将纳米物体连接到外部电气系统的装置以及用于制造该装置的方法。 根据本发明，其特别适用于分子表征，产生包括以下的器件：上层，其具有要连接到纳米物体的上接触焊盘; 下层，配有要连接到外部电气系统的下接触焊盘; 在所述下层之上，包括与所述下垫接触的电通孔的接合层; 并且在所述接合层和所述上层之间，具有至少两层配备有导线和电气通孔的层，用于将所述上焊盘连接到所述下焊盘。

公开(公告)号：US20120161333A1

公开(公告)日：2012-06-28

申请号：US13311146

申请日：2011-12-05

申请人： Aurelie THUAIRE ,  Xavier Baillin ,  Nicolas Sillon

发明人： Aurelie THUAIRE ,  Xavier Baillin ,  Nicolas Sillon

IPC分类号： H01L23/522 ,  H01L21/768

CPC分类号： H01L21/76898

摘要： Device for connecting nano-objects to external electrical systems, and method for producing the device.According to the invention, which applies in particular to molecular characterization, a device including the following is produced: an upper layer (16) equipped with upper contact pads (8) to be connected to a nano-object (2); a lower layer (18), equipped with lower contact pads (12) to be connected to an external electrical system (4); above the lower layer, a bonding layer (20) including electrical through-vias (22) in contact with the lower pads; and, between the bonding layer and the upper layer, at least two layers (22, 24) equipped with conductive lines (25) and electrical vias (26), for connecting the upper pads to the lower pads.

摘要翻译： 用于将纳米物体连接到外部电气系统的装置以及用于制造该装置的方法。 根据本发明，其特别适用于分子表征，产生了包括以下的器件：上层（16），其配备有要连接到纳米物体（2）的上接触焊盘（8）; 下层（18），其配备有连接到外部电气系统（4）的下接触焊盘（12）; 在下层上方，包括与下垫接触的电通孔（22）的接合层（20） 并且在所述接合层和所述上层之间具有至少两个配备有导线（25）和电气通孔（26）的层（22,24），用于将所述上焊盘连接到所述下焊盘。

公开(公告)号：US20090027767A1

公开(公告)日：2009-01-29

申请号：US12162841

申请日：2007-02-06

申请人： Jean-Charles Souriau ,  Nicolas Sillon ,  Jean-Pierre Joly

发明人： Jean-Charles Souriau ,  Nicolas Sillon ,  Jean-Pierre Joly

IPC分类号： B29D11/00 ,  G02B5/20 ,  B05D5/06

CPC分类号： G02B5/23 ,  G02B5/201 ,  G02C7/101 ,  G02C2202/18

摘要： A novel method makes it possible to form cavities intended to contain a liquid with determined optical properties within a film for optical use. The walls (38) of the cavities (40) are formed by plasma etching of a layer of transparent or light absorbent material (30, 34) transferred onto a microtechnological substrate, the walls (38) having a structured profile in order to limit the parasitic phenomena of light diffusion and diffraction.

摘要翻译： 一种新颖的方法使得可以形成旨在含有在用于光学用途的膜内具有确定的光学性质的液体的空腔。 空腔（40）的壁（38）通过等离子体蚀刻形成，其中转移到微技术基板上的透明或光吸收材料层（30,34），壁（38）具有结构化轮廓以限制 光扩散和衍射的寄生现象。

公开(公告)号：US08246184B2

公开(公告)日：2012-08-21

申请号：US12162841

申请日：2007-02-06

申请人： Jean-Charles Souriau ,  Nicolas Sillon ,  Jean-Pierre Joly

发明人： Jean-Charles Souriau ,  Nicolas Sillon ,  Jean-Pierre Joly

IPC分类号： G02B27/00

CPC分类号： G02B5/23 ,  G02B5/201 ,  G02C7/101 ,  G02C2202/18

摘要： A novel method makes it possible to form cavities intended to contain a liquid with determined optical properties within a film for optical use. The walls (38) of the cavities (40) are formed by plasma etching of a layer of transparent or light absorbent material (30, 34) transferred onto a microtechnological substrate, the walls (38) having a structured profile in order to limit the parasitic phenomena of light diffusion and diffraction.

摘要翻译： 一种新颖的方法使得可以形成旨在含有在用于光学用途的膜内具有确定的光学性质的液体的空腔。 空腔（40）的壁（38）通过等离子体蚀刻形成，其中转移到微技术基板上的透明或光吸收材料层（30,34），壁（38）具有结构化轮廓以限制 光扩散和衍射的寄生现象。

公开(公告)号：US20060138076A1

公开(公告)日：2006-06-29

申请号：US10536890

申请日：2003-12-18

申请人： Philippe Robert ,  France Michel ,  Catherine Maeder-Pachurka ,  Nicolas Sillon

发明人： Philippe Robert ,  France Michel ,  Catherine Maeder-Pachurka ,  Nicolas Sillon

IPC分类号： B44C1/22

CPC分类号： G01R3/00 ,  B33Y80/00 ,  B81B2203/0118 ,  B81C1/00611 ,  B81C2201/0108 ,  B81C2201/0125 ,  G01R1/0483 ,  G01R1/06711 ,  G01R1/06716 ,  G01R1/06727 ,  G01R1/06733 ,  G01R1/07342 ,  H01L23/4822 ,  H01L24/72 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3025 ,  H01R12/52 ,  H01R13/24 ,  H01R13/2407 ,  H05K3/4092 ,  H05K7/1069 ,  H01L2924/00

摘要： Production process of a flat suspended micro-structure using a sacrificial layer of polymer material and component obtained thereby The process successively comprises deposition of a sacrificial layer (2) of polymer material, deposition, on at least a part of the substrate (1) and of the front face of the sacrificial layer (2), of an embedding layer (6), the thickness whereof is larger than that of the sacrificial layer (2), and planarization so that the front faces of the sacrificial layer (2) and of the embedding layer (6) form a common flat surface. A formation layer (3) of a suspended structure (5) is deposited on the front face of the common flat surface. Planarization can comprise chemical mechanical polishing and etching of the embedding layer (6). Etching of the sacrificial layer (2) can be performed by means of a mask formed on the front face of a layer of polymer material eliminated during the planarization step.

摘要翻译： 使用聚合物材料的牺牲层和由此获得的部件的扁平悬浮微结构的制造方法该方法依次包括在基底（1）的至少一部分上沉积聚合物材料的牺牲层（2），沉积 （2）的牺牲层（2）的前表面，其厚度大于牺牲层（2）的厚度，并且平坦化，使得牺牲层（2）的前表面和 的嵌入层（6）形成共同的平坦表面。 悬挂结构（5）的形成层（3）沉积在公共平坦表面的前表面上。 平面化可以包括化学机械抛光和蚀刻嵌入层（6）。 牺牲层（2）的蚀刻可以通过形成在平坦化步骤期间消除的聚合物材料层的正面上的掩模进行。

公开(公告)号：US07648855B2

公开(公告)日：2010-01-19

申请号：US11573207

申请日：2005-08-10

申请人： Charlotte Gillot ,  Nicolas Sillon ,  Emmanuelle Lagoutte

发明人： Charlotte Gillot ,  Nicolas Sillon ,  Emmanuelle Lagoutte

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： B81C1/00333 ,  B81C1/0023 ,  B81C2203/0136 ,  B81C2203/0145

摘要： A process for manufacturing a device including a packaged microsystem. The manufactured device is in a form of a plane wafer, the microsystem being buried in the wafer. Therefore, the process is used to make a compound that may be used as a basis for other micro technology processes. Moreover, the process co-integrates electronic compounds when the device is being manufactured. The device is particularly suitable for MEMS, and particularly radiofrequency resonators.

摘要翻译： 一种用于制造包括封装微系统的装置的方法。 制造的器件是平面晶片的形式，微系统被埋在晶片中。 因此，该方法用于制备可用作其它微技术工艺基础的化合物。 此外，当制造装置时，该方法共同整合电子化合物。 该器件特别适用于MEMS，特别是射频谐振器。

公开(公告)号：US20080067655A1

公开(公告)日：2008-03-20

申请号：US11573207

申请日：2005-08-10

申请人： Charlotte Gillot ,  Nicolas Sillon ,  Emmanuelle Lagoutte

发明人： Charlotte Gillot ,  Nicolas Sillon ,  Emmanuelle Lagoutte

IPC分类号： H01L23/053 ,  H01L21/52

CPC分类号： B81C1/00333 ,  B81C1/0023 ,  B81C2203/0136 ,  B81C2203/0145

摘要： This invention discloses a process for manufacturing a device (44) comprising a packaged microsystem (10′): the device manufactured according to the invention is in the form of a plane wafer, the microsystem (10′) being buried in the wafer. Therefore, the process according to the invention is used to make a compound that may be used as a basis for other micro technology processes. Moreover, the process according to the invention co-integrates electronic compounds (36, 38) when the device (44) is being manufactured. The device (44) according to the invention is particularly suitable for MEMS, and particularly radiofrequency resonators.

摘要翻译： 本发明公开了一种用于制造包括封装微系统（10'）的器件（44）的方法：根据本发明制造的器件是平面晶片的形式，微系统（10'）被埋在晶片中。 因此，根据本发明的方法用于制备可用作其它微技术工艺基础的化合物。 此外，当制造装置（44）时，根据本发明的方法共同整合电子化合物（36,38）。 根据本发明的装置（44）特别适用于MEMS，特别是射频谐振器。

公开(公告)号：US20060194364A1

公开(公告)日：2006-08-31

申请号：US11288942

申请日：2005-11-28

申请人： Guillaume Bouche ,  Bernard Andre ,  Nicolas Sillon

发明人： Guillaume Bouche ,  Bernard Andre ,  Nicolas Sillon

IPC分类号： H01L21/00 ,  H01L21/50 ,  H01L23/02

CPC分类号： B81C1/00269 ,  B81C2203/019 ,  H01L23/10 ,  H01L2924/0002 ,  H01L2924/01079 ,  H01L2924/00

摘要： A process for packaging a plurality of micro-components made on the same substrate wafer, in which each micro-component is enclosed in a cavity. This process includes making a cover plate; depositing a metal layer on a face of the cover plate or on a face of the wafer; covering the wafer with the cover plate; applying a contact pressure equal to at least one bar onto the cover plate and onto the wafer; and heating the metal layer during pressing until a seal is obtained, each cavity thus being provided with a sealing area and being closed by a part of the cover plate and/or its metal layer.

摘要翻译： 一种用于包装在相同基板晶片上制成的多个微组件的方法，其中每个微组件封装在空腔中。 该方法包括制作盖板; 在所述盖板的表面上或所述晶片的表面上沉积金属层; 用盖板覆盖晶片; 将等于至少一个棒的接触压力施加到盖板上并到达晶片上; 并且在压制期间加热金属层直到获得密封，因此每个空腔设置有密封区域并由盖板和/或其金属层的一部分封闭。

公开(公告)号：US07999366B2

公开(公告)日：2011-08-16

申请号：US11288942

申请日：2005-11-28

申请人： Guillaume Bouche ,  Bernard Andre ,  Nicolas Sillon

发明人： Guillaume Bouche ,  Bernard Andre ,  Nicolas Sillon

IPC分类号： H01L23/02

CPC分类号： B81C1/00269 ,  B81C2203/019 ,  H01L23/10 ,  H01L2924/0002 ,  H01L2924/01079 ,  H01L2924/00

摘要： A process for packaging a plurality of micro-components made on the same substrate wafer, in which each micro-component is enclosed in a cavity. This process includes making a cover plate; depositing a metal layer on a face of the cover plate or on a face of the wafer; covering the wafer with the cover plate; applying a contact pressure equal to at least one bar onto the cover plate and onto the wafer; and heating the metal layer during pressing until a seal is obtained, each cavity thus being provided with a sealing area and being closed by a part of the cover plate and/or its metal layer.

摘要翻译： 一种用于包装在相同基板晶片上制成的多个微组件的方法，其中每个微组件封装在空腔中。 该方法包括制作盖板; 在所述盖板的表面上或所述晶片的表面上沉积金属层; 用盖板覆盖晶片; 将等于至少一个棒的接触压力施加到盖板上并到达晶片上; 并且在压制期间加热金属层直到获得密封，因此每个空腔设置有密封区域并由盖板和/或其金属层的一部分封闭。