公开(公告)号：US20190100031A1

公开(公告)日：2019-04-04

申请号：US16040007

申请日：2018-07-19

申请人： Hideaki NISHIMURA ,  Toshihiro YOSHINUMA ,  Wataru SAKAMOTO ,  Sho SAWAHATA ,  Ken ONODERA

发明人： Hideaki NISHIMURA ,  Toshihiro YOSHINUMA ,  Wataru SAKAMOTO ,  Sho SAWAHATA ,  Ken ONODERA

IPC分类号： B41J11/00 ,  B41J29/377 ,  B41J2/14 ,  B41F23/04

CPC分类号： B41J11/002 ,  B41F23/0443 ,  B41J2/1408 ,  B41J29/377 ,  B41J2202/08

摘要： A drying device includes a plurality of blowers to blow air onto an object to be dried, the plurality of blowers being disposed along a direction of conveyance of the object to be dried, and a plurality of heaters to heat air inside the plurality of blowers. Each of the plurality of blowers includes an elongated nozzle arranged along a nozzle direction perpendicular to the direction of conveyance of the object to be dried, and an airflow generator to generate airflow to be blown from the elongated nozzle. The plurality of blowers includes a first blower including the airflow generator at a first end of the first blower in the nozzle direction and a second blower including the airflow generator at a second end of the second blower opposite the first end in the nozzle direction.

公开(公告)号：US20180009237A1

公开(公告)日：2018-01-11

申请号：US15641634

申请日：2017-07-05

申请人： Wataru SAKAMOTO ,  Ken ONODERA ,  Toshihiro YOSHINUMA

发明人： Wataru SAKAMOTO ,  Ken ONODERA ,  Toshihiro YOSHINUMA

IPC分类号： B41J11/00

CPC分类号： B41J11/002

摘要： A drying device includes a heater, a supporter, a controller, and a temperature detector. The heater heats a medium. The supporter is disposed opposite the heater to support the medium. The controller turns on the heater while the medium is conveyed, and turns off the heater when the medium is stopped. The temperature detector detects a temperature of the supporter. The controller is connected to the temperature detector to turn off the heater when the temperature detected with the temperature detector is a predetermined temperature or higher.

公开(公告)号：US20180022114A1

公开(公告)日：2018-01-25

申请号：US15652478

申请日：2017-07-18

申请人： Wataru SAKAMOTO ,  Toshihiro YOSHINUMA

发明人： Wataru SAKAMOTO ,  Toshihiro YOSHINUMA

IPC分类号： B41J11/00

CPC分类号： B41J11/002 ,  B41F23/0459 ,  B41F23/0486 ,  B41J11/0095 ,  B41M7/00 ,  F26B3/18 ,  G03G15/2053

摘要： A drying device includes a roller, and the drying device is for drying a recording medium conveyed by rotation of the roller. The drying device includes a first heating source and second heating source included inside the roller; first and second temperature detectors for respectively detecting a temperature of a first region on a surface of the roller and a temperature of a second region on the surface of the roller; and a heating controller that controls heating and termination of the heating by the first heating source and/or the second heating source, wherein, upon detecting that a temperature of one region of the first region and the second region is higher than or equal to a predetermined temperature, the heating controller terminates heating by one heating source corresponding to the other region.

公开(公告)号：US20120126303A1

公开(公告)日：2012-05-24

申请号：US13237425

申请日：2011-09-20

申请人： Fumitaka ARAI ,  Wataru SAKAMOTO ,  Fumie KIKUSHIMA ,  Hiroyuki NITTA

发明人： Fumitaka ARAI ,  Wataru SAKAMOTO ,  Fumie KIKUSHIMA ,  Hiroyuki NITTA

IPC分类号： H01L29/788 ,  H01L21/28

CPC分类号： H01L29/42336 ,  H01L21/76224 ,  H01L21/764 ,  H01L21/7682 ,  H01L21/823481 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7881

摘要： According to one embodiment, a part of a buried insulating film buried in a trench is removed; accordingly, an air gap is formed between adjacent floating gate electrodes in a word line direction, and the air gap is formed continuously along the trench in a manner of sinking below a control gate electrode.

摘要翻译： 根据一个实施例，去除埋在沟槽中的埋入绝缘膜的一部分; 因此，在字线方向上在相邻的浮置栅电极之间形成气隙，并且沿着沟槽以沉没在控制栅电极下方的方式连续地形成气隙。

公开(公告)号：US20100320527A1

公开(公告)日：2010-12-23

申请号：US12792378

申请日：2010-06-02

申请人： Takayuki OKAMURA ,  Noboru OOIKE ,  Wataru SAKAMOTO ,  Takashi IZUMIDA

发明人： Takayuki OKAMURA ,  Noboru OOIKE ,  Wataru SAKAMOTO ,  Takashi IZUMIDA

IPC分类号： H01L29/792 ,  H01L21/28

CPC分类号： H01L27/11565 ,  H01L21/28282 ,  H01L27/11568

摘要： A nonvolatile semiconductor memory device according to embodiment includes: a semiconductor substrate having an upper portion being partitioned into a plurality of semiconductor portions extending in a first direction; a charge storage film provided on the semiconductor portion; a word-line electrode provided on the semiconductor substrate and extending in a second direction intersecting with the first direction; and a pair of selection gate electrodes provided on both sides of the word-line electrode in the first direction on the semiconductor substrate and extending in the second direction, a shortest distance between a corner portion of each of the semiconductor portions and each of the selection gate electrodes being longer than a shortest distance between the corner portion of the semiconductor portion and the word-line electrode in a cross section parallel to the second direction.

摘要翻译： 根据实施例的非易失性半导体存储器件包括：半导体衬底，其具有被分隔成沿第一方向延伸的多个半导体部分的上部; 设置在半导体部分上的电荷存储膜; 字线电极，其设置在所述半导体基板上并沿与所述第一方向交叉的第二方向延伸; 以及一对选择栅电极，其设置在所述半导体基板上的所述字线电极的所述第一方向的两侧，并且沿所述第二方向延伸，所述半导体部分的每个的角部与所述选择中的每一个之间的最短距离 栅电极比与半导体部分的角部和字线电极之间的平行于第二方向的截面中的最短距离更长。

公开(公告)号：US20130207175A1

公开(公告)日：2013-08-15

申请号：US13589517

申请日：2012-08-20

申请人： Wataru SAKAMOTO

发明人： Wataru SAKAMOTO

IPC分类号： H01L21/3205 ,  H01L21/82 ,  H01L27/088

CPC分类号： H01L21/32053 ,  H01L21/28273 ,  H01L21/764 ,  H01L21/82 ,  H01L27/088 ,  H01L27/11529 ,  H01L29/66825

摘要： A nonvolatile semiconductor storage device including a first transistor comprising a first gate electrode including a charge storage layer, an interelectrode insulating film, and a control electrode layer; a second transistor comprising a second gate electrode including a lower electrode, an upper electrode, and an upper silicide portion above the upper electrode; and a third transistor comprising a third gate electrode including a lower electrode, an upper electrode, and an upper silicide portion above the upper electrode; wherein the lower electrodes of the second and the third gate electrodes have a first side and a second side taken along a length direction of the second and the third gate electrodes, the lower electrodes of the second and the third gate electrodes including a lower silicide portion in which at least the first side of the lower electrodes are partially silicided.

摘要翻译： 一种非易失性半导体存储装置，包括：第一晶体管，包括包含电荷存储层的第一栅电极，电极间绝缘膜和控制电极层; 第二晶体管，包括在上电极上方包括下电极，上电极和上硅化物部分的第二栅电极; 以及第三晶体管，包括在所述上电极上方包括下电极，上电极和上硅化物部分的第三栅电极; 其中所述第二和第三栅电极的下电极具有沿着所述第二和第三栅电极的长度方向截取的第一侧和第二侧，所述第二和第三栅电极的下电极包括下硅化物部分 其中至少第一侧的下部电极部分地被硅化。

公开(公告)号：US20120213006A1

公开(公告)日：2012-08-23

申请号：US13401126

申请日：2012-02-21

申请人： Ryosuke ISOMURA ,  Wataru SAKAMOTO ,  Hiroyuki NITTA

发明人： Ryosuke ISOMURA ,  Wataru SAKAMOTO ,  Hiroyuki NITTA

IPC分类号： G11C16/04 ,  H01L27/088 ,  H01L21/764

CPC分类号： H01L27/11524 ,  G11C16/0483 ,  H01L21/764

摘要： A semiconductor storage device according to an embodiment comprises a memory cell string in which a plurality of memory cells each having a gate are serially connected to each other. A selective transistor is connected to an end memory cell at an end of the memory cell string. A sidewall film covers a side surface of a gate of the end memory cell and a side surface of a gate of the selective transistor between the end memory cell and the selective transistor. An air gap is provided between the sidewall film of the end memory cell and the sidewall film of the selective transistor,

摘要翻译： 根据实施例的半导体存储装置包括其中多个具有栅极的存储单元彼此串联连接的存储单元串。 选择晶体管连接到存储单元串末端的端存储单元。 侧壁膜覆盖端部存储单元的栅极的侧表面和在端部存储单元和选择晶体管之间的选择性晶体管的栅极的侧表面。 在端部存储单元的侧壁膜和选择性晶体管的侧壁膜之间设置气隙，

公开(公告)号：US20110193151A1

公开(公告)日：2011-08-11

申请号：US12821689

申请日：2010-06-23

申请人： Wataru SAKAMOTO

发明人： Wataru SAKAMOTO

IPC分类号： H01L29/788

CPC分类号： H01L29/42324 ,  G11C16/0466 ,  G11C16/0483 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11529 ,  H01L27/11548 ,  H01L27/11575 ,  H01L29/4234

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor substrate including a first region in which a memory cell transistor is arranged, a second region in which an electrode that extracts a word line electrically connected to the memory cell transistor is arranged, and a third region in which a peripheral transistor is arranged, the semiconductor substrate including an element isolation layer which separates adjacent active regions, first active regions provided in the first region and each having a first width, second active regions provided in the second region and each having a second width greater than the first width, third active regions provided in the third region and each having a third with greater than the first width. An upper surface of an element isolation layer in the second region is higher than that of an element isolation layer in the first region.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括：半导体衬底，包括其中布置有存储单元晶体管的第一区域;第二区域，其中布置提取与存储单元晶体管电连接的字线的电极;以及 其中配置有外围晶体管的第三区域，所述半导体衬底包括分隔相邻有源区的元件隔离层，设置在所述第一区域中的每一个具有第一宽度的第一有源区，并且每个具有第一宽度，所述第二有源区设置在所述第二区中， 具有大于第一宽度的第二宽度，设置在第三区域中的每一个具有大于第一宽度的第三有效区域。 第二区域中的元件隔离层的上表面高于第一区域中的元件隔离层的上表面。

公开(公告)号：US20100019310A1

公开(公告)日：2010-01-28

申请号：US12405544

申请日：2009-03-17

申请人： Wataru SAKAMOTO

发明人： Wataru SAKAMOTO

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7926

摘要： A semiconductor memory device includes: a semiconductor substrate; a stacked body provided on the semiconductor substrate and having a plurality of insulator layers and a plurality of conductive layers alternately stacked; a semiconductor layer provided inside a through-hole formed so as to pass through the stacked body and extending in a stacking direction of the insulator layers and the conductive layers; and a charge trap layer provided between the conductive layer and the semiconductor layer. A lower part in the semiconductor layer is narrower than an upper part therein, and at least the lowermost layer in the conductive layers is thinner than the uppermost layer therein.

摘要翻译： 半导体存储器件包括：半导体衬底; 设置在所述半导体基板上并具有交替层叠的多个绝缘体层和多个导电层的层叠体; 设置在通孔内的半导体层，其形成为穿过所述层叠体并沿所述绝缘体层和所述导电层的层叠方向延伸; 以及设置在导电层和半导体层之间的电荷陷阱层。 半导体层的下部比其上部窄，并且导电层中的至少最下层比其中最上层薄。

公开(公告)号：US20120069669A1

公开(公告)日：2012-03-22

申请号：US13237320

申请日：2011-09-20

申请人： Wataru SAKAMOTO ,  Fumitaka Arai

发明人： Wataru SAKAMOTO ,  Fumitaka Arai

IPC分类号： G11C16/10 ,  H01L21/762

CPC分类号： G11C16/0483 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/3418 ,  H01L21/28273 ,  H01L27/11524

摘要： A nonvolatile semiconductor storage device is disclosed. The device includes a cell group having a first memory cell and a second memory cell located first directionally adjacent to the first memory cell, and a programming circuit. The first memory cell is used for data retention and the second memory cell is used for adjustment of a threshold voltage of the first memory cell. The programming circuit is configured to program the first memory cell by applying voltage to the second memory cell to control the threshold voltage of the first memory cell to be higher than a first threshold voltage.

摘要翻译： 公开了一种非易失性半导体存储装置。 该设备包括具有第一存储器单元的单元组和位于第一定向相邻于第一存储单元的第二存储单元，以及编程电路。 第一存储单元用于数据保持，第二存储单元用于调整第一存储单元的阈值电压。 编程电路被配置为通过向第二存储器单元施加电压来对第一存储单元进行编程，以将第一存储单元的阈值电压控制为高于第一阈值电压。