公开(公告)号：US08952430B2

公开(公告)日：2015-02-10

申请号：US13703284

申请日：2011-06-02

申请人： Hidefumi Takaya ,  Hideo Matsuki ,  Naohiro Suzuki ,  Tsuyoshi Ishikawa

发明人： Hidefumi Takaya ,  Hideo Matsuki ,  Naohiro Suzuki ,  Tsuyoshi Ishikawa

IPC分类号： H01L29/76 ,  H01L29/16 ,  H01L29/49 ,  H01L29/40 ,  H01L29/739 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423

CPC分类号： H01L29/1608 ,  H01L21/046 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/49 ,  H01L29/66068 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813

摘要： The present application relates to technology for improving a withstand voltage of a semiconductor device. The semiconductor device includes a termination area that surrounds a cell area. The cell area is provided with a plurality of main trenches. The termination area is provided with one or more termination trenches surrounding the cell area. A termination trench is disposed at an innermost circumference of one or more termination trenches. A body region is disposed on a surface of a drift region. Each main trench reaches the drift region. A gate electrode is provided within each main trench. The termination trench reaches the drift region. Sidewalls and a bottom surface of the termination trench are covered with a insulating layer. A surface of the insulating layer covering the bottom surface of the termination trench is covered with a buried electrode. A gate potential is applied to the buried electrode.

摘要翻译： 本申请涉及用于提高半导体器件耐受电压的技术。 半导体器件包括围绕单元区域的终止区域。 单元区域设置有多个主沟槽。 终端区域设置有围绕单元区域的一个或多个终止沟槽。 终端沟槽设置在一个或多个端接沟槽的最内圆周处。 体区域设置在漂移区域的表面上。 每个主沟槽到达漂移区域。 在每个主沟槽内设置栅电极。 端接沟槽到达漂移区域。 侧壁和终端沟槽的底表面被绝缘层覆盖。 覆盖终端沟槽的底面的绝缘层的表面被掩埋电极覆盖。 将栅极电位施加到掩埋电极。

公开(公告)号：US20140252465A1

公开(公告)日：2014-09-11

申请号：US14352142

申请日：2012-10-17

申请人： Hidefumi Takaya ,  Hideo Matsuki ,  Naohiro Suzuki ,  Tsuyoshi Ishikawa ,  Narumasa Soejima ,  Yukihiko Watanabe

发明人： Hidefumi Takaya ,  Hideo Matsuki ,  Naohiro Suzuki ,  Tsuyoshi Ishikawa ,  Narumasa Soejima ,  Yukihiko Watanabe

IPC分类号： H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L29/78

CPC分类号： H01L29/4236 ,  H01L21/047 ,  H01L21/28008 ,  H01L21/823487 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/1608 ,  H01L29/41741 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/66666 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/7827

摘要： A semiconductor device has a semiconductor substrate including a body region, a drift region, a trench that extends from a surface of the semiconductor substrate into the drift region through the body region, and a source region located adjacent to the trench in a range exposed to the surface of the semiconductor substrate, the source region being isolated from the drift region by the body region. A specific layer is disposed on a bottom of the trench, and it has a characteristic of forming a depletion layer at a junction between the specific layer and the drift region. An insulating layer covers an upper surface of the specific layer and a sidewall of the trench. A conductive portion is formed on a part of the side wall of the trench. The conductive portion is joined to the specific layer, and reaches the surface of the semiconductor substrate.

摘要翻译： 半导体器件具有半导体衬底，其包括体区，漂移区，从半导体衬底的表面延伸通过体区的漂移区的沟槽，以及与暴露于 半导体衬底的表面，源区域通过身体区域与漂移区隔离。 特定层设置在沟槽的底部，并且具有在特定层和漂移区之间的结处形成耗尽层的特征。 绝缘层覆盖特定层的上表面和沟槽的侧壁。 导电部分形成在沟槽的侧壁的一部分上。 导电部分连接到特定层，并到达半导体衬底的表面。

公开(公告)号：US20130075760A1

公开(公告)日：2013-03-28

申请号：US13703284

申请日：2011-06-02

申请人： Hidefumi Takaya ,  Hideo Matsuki ,  Naohiro Suzuki ,  Tsuyoshi Ishikawa

发明人： Hidefumi Takaya ,  Hideo Matsuki ,  Naohiro Suzuki ,  Tsuyoshi Ishikawa

IPC分类号： H01L29/16 ,  H01L29/49

CPC分类号： H01L29/1608 ,  H01L21/046 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/49 ,  H01L29/66068 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813

摘要： The present application relates to technology for improving a withstand voltage of a semiconductor device. The semiconductor device includes a termination area that surrounds a cell area. The cell area is provided with a plurality of main trenches. The termination area is provided with one or more termination trenches surrounding the cell area. A termination trench is disposed at an innermost circumference of one or more termination trenches. A body region is disposed on a surface of a drift region. Each main trench reaches the drift region. A gate electrode is provided within each main trench. The termination trench reaches the drift region. Sidewalls and a bottom surface of the termination trench are covered with a insulating layer. A surface of the insulating layer covering the bottom surface of the termination trench is covered with a buried electrode. A gate potential is applied to the buried electrode.

摘要翻译： 本申请涉及用于提高半导体器件耐受电压的技术。 半导体器件包括围绕单元区域的终止区域。 单元区域设置有多个主沟槽。 终端区域设置有围绕单元区域的一个或多个终止沟槽。 终端沟槽设置在一个或多个端接沟槽的最内圆周处。 体区域设置在漂移区域的表面上。 每个主沟槽到达漂移区域。 在每个主沟槽内设置栅电极。 端接沟槽到达漂移区域。 侧壁和终端沟槽的底表面被绝缘层覆盖。 覆盖终端沟槽的底面的绝缘层的表面被掩埋电极覆盖。 将栅极电位施加到掩埋电极。

公开(公告)号：US09276075B2

公开(公告)日：2016-03-01

申请号：US14352142

申请日：2012-10-17

申请人： Hidefumi Takaya ,  Hideo Matsuki ,  Naohiro Suzuki ,  Tsuyoshi Ishikawa ,  Narumasa Soejima ,  Yukihiko Watanabe

发明人： Hidefumi Takaya ,  Hideo Matsuki ,  Naohiro Suzuki ,  Tsuyoshi Ishikawa ,  Narumasa Soejima ,  Yukihiko Watanabe

IPC分类号： H01L29/78 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/417 ,  H01L29/66 ,  H01L29/06 ,  H01L21/28 ,  H01L21/04 ,  H01L29/16

CPC分类号： H01L29/4236 ,  H01L21/047 ,  H01L21/28008 ,  H01L21/823487 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/1608 ,  H01L29/41741 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/66666 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/7827

摘要： A semiconductor device has a semiconductor substrate including a body region, a drift region, a trench that extends from a surface of the semiconductor substrate into the drift region through the body region, and a source region located adjacent to the trench in a range exposed to the surface of the semiconductor substrate, the source region being isolated from the drift region by the body region. A specific layer is disposed on a bottom of the trench, and it has a characteristic of forming a depletion layer at a junction between the specific layer and the drift region. An insulating layer covers an upper surface of the specific layer and a sidewall of the trench. A conductive portion is formed on a part of the side wall of the trench. The conductive portion is joined to the specific layer, and reaches the surface of the semiconductor substrate.

摘要翻译： 半导体器件具有半导体衬底，其包括体区，漂移区，从半导体衬底的表面延伸通过体区的漂移区的沟槽，以及与暴露于 半导体衬底的表面，源区域通过身体区域与漂移区隔离。 特定层设置在沟槽的底部，并且具有在特定层和漂移区之间的结处形成耗尽层的特征。 绝缘层覆盖特定层的上表面和沟槽的侧壁。 导电部分形成在沟槽的侧壁的一部分上。 导电部分连接到特定层，并到达半导体衬底的表面。

公开(公告)号：US08618555B2

公开(公告)日：2013-12-31

申请号：US13117575

申请日：2011-05-27

申请人： Naohiro Suzuki ,  Hideo Matsuki ,  Masahiro Sugimoto ,  Hidefumi Takaya ,  Jun Morimoto ,  Tsuyoshi Ishikawa ,  Narumasa Soejima ,  Yukihiko Watanabe

发明人： Naohiro Suzuki ,  Hideo Matsuki ,  Masahiro Sugimoto ,  Hidefumi Takaya ,  Jun Morimoto ,  Tsuyoshi Ishikawa ,  Narumasa Soejima ,  Yukihiko Watanabe

IPC分类号： H01L29/66

CPC分类号： H01L29/7813 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068

摘要： The silicon carbide semiconductor device includes a substrate, a drift layer, a base region, a source region, a trench, a gate insulating layer, a gate electrode, a source electrode, a drain electrode, and a deep layer. The deep layer is disposed under the base region and is located to a depth deeper than the trench. The deep layer is divided into a plurality of portions in a direction that crosses a longitudinal direction of the trench. The portions include a group of portions disposed at positions corresponding to the trench and arranged at equal intervals in the longitudinal direction of the trench. The group of portions surrounds corners of a bottom of the trench.

摘要翻译： 碳化硅半导体器件包括衬底，漂移层，基极区域，源极区域，沟槽，栅极绝缘层，栅极电极，源极电极，漏极电极和深层。 深层设置在基底区域下方并且位于比沟槽更深的深度。 深层在与沟槽的纵向方向交叉的方向上分成多个部分。 这些部分包括设置在与沟槽相对应的位置处的一组部分，其在沟槽的纵向方向上以相等的间隔布置。 该组部分围绕沟槽的底部的角落。

公开(公告)号：US20120319136A1

公开(公告)日：2012-12-20

申请号：US13581497

申请日：2012-02-06

申请人： Masato Noborio ,  Kensaku Yamamoto ,  Hideo Matsuki ,  Hidefumi Takaya ,  Masahiro Sugimoto ,  Narumasa Soejima ,  Tsuyoshi Ishikawa ,  Yukihiko Watanabe

发明人： Masato Noborio ,  Kensaku Yamamoto ,  Hideo Matsuki ,  Hidefumi Takaya ,  Masahiro Sugimoto ,  Narumasa Soejima ,  Tsuyoshi Ishikawa ,  Yukihiko Watanabe

IPC分类号： H01L29/24 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66348 ,  H01L29/7397

摘要： A SiC device includes an inversion type MOSFET having: a substrate, a drift layer, and a base region stacked in this order; source and contact regions in upper portions of the base region; a trench penetrating the source and base regions; a gate electrode on a gate insulating film in the trench; a source electrode coupled with the source and base region; a drain electrode on a back of the substrate; and multiple deep layers in an upper portion of the drift layer deeper than the trench. Each deep layer has an impurity concentration distribution in a depth direction, and an inversion layer is provided in a portion of the deep layer on the side of the trench under application of the gate voltage.

摘要翻译： SiC器件包括反转型MOSFET，其具有：依次堆叠的衬底，漂移层和基极区域; 源极和接触区域在基极区域的上部; 穿透源区和基区的沟槽; 沟槽中的栅极绝缘膜上的栅电极; 源极与源极和基极区域耦合; 位于衬底背面的漏电极; 以及在漂移层的上部比沟槽更深的多个深层。 每个深层在深度方向上具有杂质浓度分布，并且在施加栅极电压下在沟槽侧的深层的一部分中设置反转层。

公开(公告)号：US20140175459A1

公开(公告)日：2014-06-26

申请号：US13994855

申请日：2012-02-06

申请人： Kensaku Yamamoto ,  Masato Noborio ,  Hideo Matsuki ,  Hidefumi Takaya ,  Masahiro Sugimoto ,  Narumasa Soejima ,  Tsuyoshi Ishikawa ,  Yukihiko Watanabe

发明人： Kensaku Yamamoto ,  Masato Noborio ,  Hideo Matsuki ,  Hidefumi Takaya ,  Masahiro Sugimoto ,  Narumasa Soejima ,  Tsuyoshi Ishikawa ,  Yukihiko Watanabe

IPC分类号： H01L29/78 ,  H01L29/16 ,  H01L29/66

CPC分类号： H01L29/7813 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66348 ,  H01L29/7397

摘要： A SiC semiconductor device includes: a semiconductor switching element having: a substrate, a drift layer and a base region stacked in this order; a source region and a contact region in the base region; a trench extending from a surface of the source region to penetrate the base region; a gate electrode on a gate insulating film in the trench; a source electrode electrically coupled with the source region and the base region; a drain electrode on a back side of the substrate; and multiple deep layers in an upper portion of the drift layer deeper than the trench. Each deep layer has upper and lower portions. A width of the upper portion is smaller than the lower portion.

摘要翻译： SiC半导体器件包括：半导体开关元件，其具有：依次层叠的基板，漂移层和基极区域; 源极区域和基极区域中的接触区域; 从源极区域的表面延伸以穿透基部区域的沟槽; 沟槽中的栅极绝缘膜上的栅电极; 源极，与源极区域和基极区域电耦合; 位于所述基板的背面的漏电极; 以及在漂移层的上部比沟槽更深的多个深层。 每个深层具有上部和下部。 上部的宽度小于下部。

公开(公告)号：US08193564B2

公开(公告)日：2012-06-05

申请号：US12379076

申请日：2009-02-12

申请人： Naohiro Suzuki ,  Eiichi Okuno ,  Hideo Matsuki

发明人： Naohiro Suzuki ,  Eiichi Okuno ,  Hideo Matsuki

IPC分类号： H01L29/71

CPC分类号： H01L29/7813 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0661 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7811 ,  H01L29/7828

摘要： A silicon carbide semiconductor device includes a substrate, a drift layer located on a first surface of the substrate, a base region located on the drift layer, a source region located on the base region, a trench penetrating the source region and the base region to the drift layer, a channel layer located in the trench, a gate insulating layer located on the channel layer, a gate electrode located on the gate insulating layer, a source electrode electrically coupled with the source region and the base region, a drain electrode located on a second surface of the substrate, and a deep layer. The deep layer is located under the base region, extends to a depth deeper than the trench and is formed along an approximately normal direction to a sidewall of the trench.

摘要翻译： 碳化硅半导体器件包括衬底，位于衬底的第一表面上的漂移层，位于漂移层上的基极区域，位于基极区域上的源极区域，穿透源极区域和基极区域的沟槽 漂移层，位于沟槽中的沟道层，位于沟道层上的栅极绝缘层，位于栅极绝缘层上的栅电极，与源区和基极区电耦合的源电极，位于 在衬底的第二表面上和深层。 深层位于基底区域下方，延伸到比沟槽更深的深度，并且沿着大致正常的方向形成在沟槽的侧壁上。

公开(公告)号：US20090200559A1

公开(公告)日：2009-08-13

申请号：US12379076

申请日：2009-02-12

申请人： Naohiro Suzuki ,  Eiichi Okuno ,  Hideo Matsuki

发明人： Naohiro Suzuki ,  Eiichi Okuno ,  Hideo Matsuki

IPC分类号： H01L29/15

CPC分类号： H01L29/7813 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0661 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7811 ,  H01L29/7828

摘要： A silicon carbide semiconductor device includes a substrate, a drift layer located on a first surface of the substrate, a base region located on the drift layer, a source region located on the base region, a trench penetrating the source region and the base region to the drift layer, a channel layer located in the trench, a gate insulating layer located on the channel layer, a gate electrode located on the gate insulating layer, a source electrode electrically coupled with the source region and the base region, a drain electrode located on a second surface of the substrate, and a deep layer. The deep layer is located under the base region, extends to a depth deeper than the trench and is formed along an approximately normal direction to a sidewall of the trench.

摘要翻译： 碳化硅半导体器件包括衬底，位于衬底的第一表面上的漂移层，位于漂移层上的基极区域，位于基极区域上的源极区域，穿透源极区域和基极区域的沟槽 漂移层，位于沟槽中的沟道层，位于沟道层上的栅极绝缘层，位于栅极绝缘层上的栅电极，与源区和基极区电耦合的源电极，位于 在衬底的第二表面上和深层。 深层位于基底区域下方，延伸到比沟槽更深的深度，并且沿着大致正常的方向形成在沟槽的侧壁上。

公开(公告)号：US07855412B2

公开(公告)日：2010-12-21

申请号：US12453520

申请日：2009-05-14

申请人： Hideo Matsuki ,  Eiichi Okuno ,  Naohiro Suzuki

发明人： Hideo Matsuki ,  Eiichi Okuno ,  Naohiro Suzuki

IPC分类号： H01L27/108 ,  H01L29/76

CPC分类号： H01L21/0465 ,  H01L21/0475 ,  H01L29/1608 ,  H01L29/66068

摘要： An SiC semiconductor device includes a substrate, a drift layer disposed on a first surface of the substrate, a base region disposed above the drift layer, a source region disposed above the base region, a trench penetrating the source region and the base region to the drift layer, a gate insulating layer disposed on a surface of the trench, a gate electrode disposed on a surface of the gate insulating layer, a first electrode electrically coupled with the source region and the base region, a second electrode disposed on the second surface of the substrate, and a second conductivity-type layer disposed at a portion of the base region located under the source region. The second conductivity-type layer has the second conductivity type and has an impurity concentration higher than the base region.

摘要翻译： SiC半导体器件包括衬底，设置在衬底的第一表面上的漂移层，设置在漂移层上方的基极区域，设置在基极区域上方的源极区域，穿透源极区域和基极区域的沟槽 漂移层，设置在沟槽表面上的栅极绝缘层，设置在栅极绝缘层的表面上的栅极电极，与源极区域和基极区域电耦合的第一电极，设置在第二表面上的第二电极 以及设置在位于源极区域下方的基极区域的一部分的第二导电型层。 第二导电型层具有第二导电类型并且具有高于基极区的杂质浓度。