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    Source drain implant during ONO formation for improved isolation of SONOS devices
    1.
    发明授权
    Source drain implant during ONO formation for improved isolation of SONOS devices 有权
    在ONO形成期间的源极漏极注入，以改善SONOS器件的隔离

    公开(公告)号：US06436768B1

    公开(公告)日：2002-08-20

    申请号：US09893279

    申请日：2001-06-27

    申请人： Jean Yee-Mei Yang ,  Mark T. Ramsbey ,  Emmanuil Manos Lingunis ,  Yider Wu ,  Tazrien Kamal ,  Yi He ,  Edward Hsia ,  Hidehiko Shiraiwa

    发明人： Jean Yee-Mei Yang ,  Mark T. Ramsbey ,  Emmanuil Manos Lingunis ,  Yider Wu ,  Tazrien Kamal ,  Yi He ,  Edward Hsia ,  Hidehiko Shiraiwa

    IPC分类号： H01L21336

    CPC分类号： H01L21/2652 ,  H01L21/2658 ,  H01L27/11568 ,  H01L29/66833

    摘要： One aspect of the present invention relates to a method of forming a SONOS type non-volatile semiconductor memory device, involving forming a first layer of a charge trapping dielectric on a semiconductor substrate; forming a second layer of the charge trapping dielectric over the first layer of the charge trapping dielectric on the semiconductor substrate; optionally at least partially forming a third layer of the charge trapping dielectric over the second layer of the charge trapping dielectric on the semiconductor substrate; optionally removing the third layer of the charge trapping dielectric; forming a source/drain mask over the charge trapping dielectric; implanting a source/drain implant through the charge trapping dielectric into the semiconductor substrate; optionally removing the third layer of the charge trapping dielectric; and one of forming the third layer of the charge trapping dielectric over the second layer of the charge trapping dielectric on the semiconductor substrate, reforming the third layer of the charge trapping dielectric over the second layer of the charge trapping dielectric on the semiconductor substrate, or forming additional material over the third layer of the charge trapping dielectric.

    摘要翻译： 本发明的一个方面涉及一种形成SONOS型非易失性半导体存储器件的方法，包括在半导体衬底上形成电荷俘获电介质的第一层; 在所述半导体衬底上的所述电荷俘获电介质的所述第一层上形成所述电荷俘获电介质的第二层; 可选地至少部分地在所述半导体衬底上的所述电荷俘获电介质的所述第二层上形成所述电荷俘获电介质的第三层; 任选地去除电荷俘获电介质的第三层; 在电荷俘获电介质上形成源极/漏极掩模; 将源极/漏极注入物通过电荷俘获电介质注入到半导体衬底中; 任选地去除电荷俘获电介质的第三层; 以及在半导体衬底上的电荷俘获电介质的第二层上形成电荷俘获电介质的第三层之一，在半导体衬底上的电荷俘获电介质的第二层上重整第三层电荷俘获电介质，或 在电荷俘获电介质的第三层上形成附加材料。

    Method for reading a non-volatile memory cell adjacent to an inactive region of a non-volatile memory cell array
    5.
    发明授权
    Method for reading a non-volatile memory cell adjacent to an inactive region of a non-volatile memory cell array 有权
    用于读取与非易失性存储单元阵列的非活动区域相邻的非易失性存储单元的方法

    公开(公告)号：US06771545B1

    公开(公告)日：2004-08-03

    申请号：US10353558

    申请日：2003-01-29

    申请人： Edward Hsia ,  Eric Ajimine ,  Darlene G. Hamilton ,  Pauling Chen ,  Ming-Huei Shieh ,  Mark W. Randolph ,  Edward Runnion ,  Yi He

    发明人： Edward Hsia ,  Eric Ajimine ,  Darlene G. Hamilton ,  Pauling Chen ,  Ming-Huei Shieh ,  Mark W. Randolph ,  Edward Runnion ,  Yi He

    IPC分类号： G11C1604

    CPC分类号： G11C29/82 ,  G11C16/0491 ,  G11C16/3404

    摘要： An array of non-volatile memory cells includes active columns of cells wherein a data pattern may be stored adjacent to damaged or inactive columns wherein data is not stored. A method of storing a data pattern and reproducing the data pattern within such an array comprises storing a charge within a selected plurality of the memory cells within the active column. The selected plurality of memory cells represents a portion of the data pattern. An inactive memory cell programming pattern is identified. The inactive memory cell programming pattern identifies all, or a selected plurality, of the memory cells in the inactive column in which a charge is to be stored for the purpose of periodically storing a charge in the memory cells first inactive column to prevent over erasure, during bulk erase, and leakage from the inactive cells to adjacent active cells. A charge is stored on the selected plurality of the memory cells in the first inactive column. The data pattern is reproduced reading each memory cell within the first active column.

    摘要翻译： 非易失性存储器单元的阵列包括有效的单元格列，其中数据模式可以存储在与不存储数据的损坏或非活动列相邻的位置。 存储数据模式并在其中再现数据模式的方法包括将电荷存储在活动列内的所选择的多个存储单元内。 所选择的多个存储单元表示数据模式的一部分。 识别非活动存储器单元编程模式。 非活动存储器单元编程模式识别要在其中存储电荷的所述非活动列中的所有或选定的多个存储单元，以便在存储单元的第一非活动列中周期性地存储电荷以防止过度擦除， 在批量擦除期间以及从非活性电池泄漏到相邻的活性电池。 在第一非活动列中的所选择的多个存储器单元上存储电荷。 读取在第一活动列内的每个存储单元的数据模式。

    Method of programming a dual cell memory device
    7.
    发明授权
    Method of programming a dual cell memory device 失效
    编程双单元存储器件的方法

    公开(公告)号：US06775187B1

    公开(公告)日：2004-08-10

    申请号：US10422489

    申请日：2003-04-24

    申请人： Darlene G. Hamilton ,  Edward F. Runnion ,  Edward Hsia ,  Kulachet Tanpairoj

    发明人： Darlene G. Hamilton ,  Edward F. Runnion ,  Edward Hsia ,  Kulachet Tanpairoj

    IPC分类号： G11C1604

    CPC分类号： G11C16/10 ,  G11C16/0475

    摘要： A method of programming a dual cell memory device having a first charge storing cell and second charge storing cell. The first charge storing cell can be pre-read to determine if the first charge storing cell stores an amount of charge to increase a threshold voltage of the memory device over a specified threshold voltage. If not, the second charge storing cell can be programmed with a standard program pulse. If so, the second charge storing cell can be programed with a modified program pulse.

    摘要翻译： 一种编程具有第一电荷存储单元和第二电荷存储单元的双单元存储器件的方法。 可以预先读取第一电荷存储单元，以确定第一电荷存储单元是否存储一定量的电荷以增加存储器件的阈值电压超过指定的阈值电压。 如果不是，则可以用标准编程脉冲编程第二电荷存储单元。 如果是这样，则可以用修改的编程脉冲对第二电荷存储单元进行编程。

    Azole antifungal compositions
    8.
    发明授权
    Azole antifungal compositions 有权

    公开(公告)号：US10251885B2

    公开(公告)日：2019-04-09

    申请号：US13322667

    申请日：2010-05-27

    申请人： Jon Lenn ,  Hans Hofland ,  Edward Hsia

    发明人： Jon Lenn ,  Hans Hofland ,  Edward Hsia

    IPC分类号： A61K31/517 ,  A61K9/00 ,  A61K9/70 ,  A61K45/06

    摘要： The present invention relates generally to antifugal compositions. In an embodiment, the antifungal compositions are effective for application to nails and surrounding skin, and comprise at least one volatile solvent, at least one film forming substance, and at least one pyrimidone derivative of formula I, such as albaconazole. These compositions are capable of treating an infection caused by fungi, such as onychomychosis.

    Methods to Inhibit Histone Acetyltransferase Using Glycosaminoglycans
    9.
    发明申请
    Methods to Inhibit Histone Acetyltransferase Using Glycosaminoglycans 审中-公开
    使用糖胺聚糖抑制组蛋白乙酰转移酶的方法

    公开(公告)号：US20080227752A1

    公开(公告)日：2008-09-18

    申请号：US11630078

    申请日：2005-06-28

    申请人： Matthew A. Nugent ,  Edward Hsia ,  Jo Ann Buczek-Thomas

    发明人： Matthew A. Nugent ,  Edward Hsia ,  Jo Ann Buczek-Thomas

    IPC分类号： A61K31/715 ,  A61P27/02 ,  A61P11/00 ,  A61P35/04 ,  A61P9/00

    CPC分类号： A61K31/727

    摘要： The present invention is directed to methods for inhibition of histone acetyltransferases using glycosaminoglycans. The invention is further directed to methods for treating disorders associated with hyperacetylation by administration of glycosaminoglycans to a patient in need thereof. In one preferred embodiment, the glycosaminoglycan is a heparin or heparan sulfate oligosaccharide. Studies show that removal of sulfate residues from the O-positions of either the uronic acid or the glucosamine did not eliminate the inhibitory activity of heparan sulfate. Since a majority of heparan sulfate binding proteins appear to require O-sulfation, molecules without certain O-sulfations can be used to inhibit HATs while not interacting with most known heparin-binding proteins. In addition, specific sequences of heparin/heparan sulfate can be used to specifically inhibit various HATs.

    摘要翻译： 本发明涉及使用糖胺聚糖抑制组蛋白乙酰转移酶的方法。 本发明还涉及通过向有需要的患者施用糖胺聚糖来治疗与超乙酰化相关的病症的方法。 在一个优选的实施方案中，糖胺聚糖是肝素或硫酸乙酰肝素寡糖。 研究表明，从糖醛酸或葡糖胺的O-位去除硫酸盐残留物并没有消除硫酸乙酰肝素的抑制活性。 由于大多数硫酸乙酰肝素结合蛋白似乎需要O-硫酸化，因此没有某些O-硫酸化的分子可用于抑制HAT，而不与大多数已知的肝素结合蛋白相互作用。 此外，肝素/硫酸乙酰肝素的特异性序列可用于特异性抑制各种HAT。

    Method of determining charge loss activation energy of a memory array
    10.
    发明授权
    Method of determining charge loss activation energy of a memory array 失效
    确定存储器阵列的电荷损耗激活能的方法

    公开(公告)号：US06813752B1

    公开(公告)日：2004-11-02

    申请号：US10306667

    申请日：2002-11-26

    申请人： Edward Hsia ,  Darlene G. Hamilton ,  Wei Zheng ,  Mark W. Randolph ,  Kulachet Tanpairoj

    发明人： Edward Hsia ,  Darlene G. Hamilton ,  Wei Zheng ,  Mark W. Randolph ,  Kulachet Tanpairoj

    IPC分类号： G06F1750

    CPC分类号： G11C29/50 ,  G11C16/04

    摘要： A method of determining charge loss activation for a memory array. Memory arrays are programmed with a pattern for testing charge loss. Then, respective bake times are calculated for the memory arrays to experience a given amount of charge loss at their respective bake temperatures. Then, charge loss activation energy is calculated, based on the respective bake times. In one version, the memory arrays are cycled by repeatedly erasing and reprogramming them before baking. In another embodiment, various regions of the memory arrays are programmed to a plurality of distinct delta threshold voltages before baking.

    摘要翻译： 确定存储器阵列的电荷损失激活的方法。 存储器阵列被编程用于测试电荷损失的模式。 然后，对于存储器阵列计算各自的烘烤时间，以在其各自的烘烤温度下经历给定量的电荷损失。 然后，基于相应的烘烤时间计算电荷损失激活能。 在一个版本中，通过在烘烤之前重复擦除和重新编程它们来循环存储器阵列。 在另一个实施例中，存储器阵列的各个区域在烘烤之前被编程为多个不同的增量阈值电压。