公开(公告)号：US07163860B1

公开(公告)日：2007-01-16

申请号：US10430471

申请日：2003-05-06

申请人： Tazrien Kamal ,  Yun Wu ,  Mark Ramsbey ,  Jean Yee-Mei Yang ,  Arvind Halliyal ,  Rinji Sugino ,  Hidehiko Shiraiwa ,  Fred T K Cheung

发明人： Tazrien Kamal ,  Yun Wu ,  Mark Ramsbey ,  Jean Yee-Mei Yang ,  Arvind Halliyal ,  Rinji Sugino ,  Hidehiko Shiraiwa ,  Fred T K Cheung

IPC分类号： H01L21/8247

CPC分类号： H01L21/28282 ,  H01L29/7923 ,  Y10S438/954

摘要： The present invention, in one embodiment, relates to a process for fabricating a charge trapping dielectric flash memory device including steps of providing a semiconductor substrate having formed thereon a gate stack comprising a charge trapping dielectric charge storage layer and a control gate electrode overlying the charge trapping dielectric charge storage layer; forming an oxide layer over at least the gate stack; and depositing a spacer layer over the gate stack, wherein the depositing step deposits a spacer material having a reduced hydrogen content relative to a hydrogen content of a conventional spacer material.

摘要翻译： 本发明在一个实施例中涉及一种用于制造电荷俘获电介质闪存器件的方法，该器件包括提供半导体衬底，该半导体衬底上形成有包括电荷俘获介电电荷存储层和覆盖电荷的控制栅电极 俘获介电电荷存储层; 至少在所述栅叠层上形成氧化层; 以及在所述栅极堆叠上沉积间隔层，其中所述沉积步骤沉积相对于常规间隔物材料的氢含量具有降低的氢含量的间隔物材料。

公开(公告)号：US07033957B1

公开(公告)日：2006-04-25

申请号：US10358586

申请日：2003-02-05

申请人： Hidehiko Shiraiwa ,  Tazrien Kamal ,  Mark Ramsbey ,  Inkuk Kang ,  Jaeyong Park ,  Rinji Sugino ,  Jean Y. Yang ,  Fred T K Cheung ,  Arvind Halliyal ,  Amir H. Jafarpour

发明人： Hidehiko Shiraiwa ,  Tazrien Kamal ,  Mark Ramsbey ,  Inkuk Kang ,  Jaeyong Park ,  Rinji Sugino ,  Jean Y. Yang ,  Fred T K Cheung ,  Arvind Halliyal ,  Amir H. Jafarpour

IPC分类号： H01L21/31

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L21/3144 ,  H01L29/513 ,  H01L29/792 ,  Y10S438/954

摘要： Process for reducing charge leakage in a SONOS flash memory device, including in one embodiment, forming a bottom oxide layer of an ONO structure on the semiconductor substrate to form an oxide/silicon interface having a first oxygen content adjacent the oxide/silicon interface; treating the bottom oxide layer to increase the first oxygen content to a second oxygen content adjacent the oxide/silicon interface; and depositing a nitride charge-storage layer on the bottom oxide layer. In another embodiment, process for reducing charge leakage in a SONOS flash memory device, including forming a bottom oxide layer of an ONO structure on a surface of the semiconductor substrate having an oxide/silicon interface with a super-stoichiometric oxygen content adjacent the oxide/silicon interface; and depositing a nitride charge-storage layer on the bottom oxide layer.

摘要翻译： 包括在一个实施例中，在半导体衬底上形成ONO结构的底部氧化物层以形成具有与氧化物/硅界面相邻的第一氧含量的氧化物/硅界面的方法，用于减少SONOS闪速存储器件中的电荷泄漏的方法; 处理底部氧化物层以将第一氧含量增加到邻近氧化物/硅界面的第二氧含量; 以及在底部氧化物层上沉积氮化物电荷存储层。 在另一个实施方案中，用于减少SONOS闪速存储器件中的电荷泄漏的方法，包括在半导体衬底的表面上形成具有超化学计量氧含量的氧化物/硅界面的氧化物/硅界面的氧化物/ 硅界面; 以及在底部氧化物层上沉积氮化物电荷存储层。

公开(公告)号：US06958511B1

公开(公告)日：2005-10-25

申请号：US10679774

申请日：2003-10-06

申请人： Arvind Halliyal ,  Amir H. Jafarpour ,  Hidehiko Shiraiwa ,  Tazrien Kamal ,  Mark Ramsbey ,  Jaeyong Park

发明人： Arvind Halliyal ,  Amir H. Jafarpour ,  Hidehiko Shiraiwa ,  Tazrien Kamal ,  Mark Ramsbey ,  Jaeyong Park

IPC分类号： H01L21/28 ,  H01L21/31 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/51 ,  H01L29/76 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28282 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7923

摘要： Process of fabricating multi-bit charge trapping dielectric flash memory device, including forming on a semiconductor substrate a bottom oxide layer to define a substrate/oxide interface, in which the bottom oxide layer includes a first oxygen concentration and a first nitrogen concentration; and adding a quantity of nitrogen to the bottom oxide layer, whereby the bottom oxide layer includes a first region adjacent the charge storage layer and a second region adjacent the substrate/oxide interface, the second region having a second oxygen concentration and a second nitrogen concentration, in which the second nitrogen concentration exceeds the first nitrogen concentration, provided that the second nitrogen concentration does not exceed the second oxygen concentration. In one embodiment, the first nitrogen concentration is substantially zero.

摘要翻译： 制造多位电荷俘获电介质闪存器件的方法，包括在半导体衬底上形成底部氧化物层以限定衬底/氧化物界面，其中底部氧化物层包括第一氧浓度和第一氮浓度; 并且向底部氧化物层添加一定量的氮，由此底部氧化物层包括与电荷存储层相邻的第一区域和与衬底/氧化物界面相邻的第二区域，第二区域具有第二氧浓度和第二氮浓度 其中第二氮浓度超过第一氮浓度，条件是第二氮浓度不超过第二氧浓度。 在一个实施方案中，第一氮浓度基本为零。

公开(公告)号：US06855608B1

公开(公告)日：2005-02-15

申请号：US10463643

申请日：2003-06-17

申请人： Mark Ramsbey ,  Mark W. Randolph ,  Jean Yee-Mei Yang ,  Hiroyuki Kinoshita ,  Cyrus Tabery ,  Jeff P. Erhardt ,  Tazrien Kamal ,  Jaeyong Park ,  Emmanuil H. Lingunis

发明人： Mark Ramsbey ,  Mark W. Randolph ,  Jean Yee-Mei Yang ,  Hiroyuki Kinoshita ,  Cyrus Tabery ,  Jeff P. Erhardt ,  Tazrien Kamal ,  Jaeyong Park ,  Emmanuil H. Lingunis

IPC分类号： G11C16/04 ,  H01L21/336 ,  H01L21/8246 ,  H01L27/105

CPC分类号： H01L27/11568 ,  G11C16/0475 ,  G11C16/0491 ,  H01L27/105 ,  H01L27/11573

摘要： A method of fabricating a planar architecture charge trapping dielectric memory cell array with rectangular gates comprises fabricating a multi-layer charge trapping dielectric on the surface of a substrate. The layer adjacent to the substrate may be an oxide. A polysilicon layer is deposited over the charge trapping dielectric. A word line mask is applied over the polysilicon layer to mask linear word lines in a first direction and to expose trench regions there between and the trenches are etched to expose the charge trapping dielectric in the trench regions. A bit line mask is applied over the polysilicon layer to mask gates in a second direction perpendicular to the first direction and to expose bit line regions there between and the bit lines are etched to expose the oxide in the bit line regions. The bit lines are implanted and insulating spacers are fabricated on exposed sidewalls. The oxide is removed to expose the substrate between insulating spacers in the bit line regions and a conductor is fabricated thereon to enhance conductivity of each bit line.

摘要翻译： 制造具有矩形栅极的平面架构电荷俘获介质存储单元阵列的方法包括在衬底的表面上制造多层电荷俘获电介质。 与衬底相邻的层可以是氧化物。 在电荷捕获电介质上沉积多晶硅层。 在多晶硅层上施加字线掩模以在第一方向上屏蔽线性字线并且在其间露出沟槽区域，并且蚀刻沟槽以暴露沟槽区域中的电荷俘获电介质。 将位线掩模施加在多晶硅层上以在垂直于第一方向的第二方向上屏蔽栅极，并在其间暴露位线区域，并蚀刻位线以暴露位线区域中的氧化物。 植入位线，并在暴露的侧壁上制造绝缘间隔物。 去除氧化物以在位线区域中的绝缘间隔物之间​​露出衬底，并且在其上制造导体以增强每个位线的导电性。

公开(公告)号：US06989320B2

公开(公告)日：2006-01-24

申请号：US10843289

申请日：2004-05-11

申请人： Weidong Qian ,  Mark Ramsbey ,  Jean Yee-Mei Yang ,  Sameer Haddad

发明人： Weidong Qian ,  Mark Ramsbey ,  Jean Yee-Mei Yang ,  Sameer Haddad

IPC分类号： H01L21/425

CPC分类号： H01L27/115 ,  H01L27/11568

摘要： The present invention pertains to implementing a dual poly process in forming a transistor based memory device. The process allows buried bitlines to be formed with less energy and to shallower depths than conventional bitlines to save resources and space, and to improve Vt roll-off. Oxide materials are also formed over the buried bitlines to improve (e.g., increase) a breakdown voltage between the bitlines and wordlines, thus allowing for greater discrimination between programming and erasing charges and more reliable resulting data storage. The process also facilitates a reduction in buried bitline width and thus allows bitlines to be formed closer together. As a result, more devices can be “packed” within the same or a smaller area.

摘要翻译： 本发明涉及在形成基于晶体管的存储器件中实现双重聚合工艺。 该过程允许以比常规位线更少的能量和更浅的深度形成掩埋位线，以节省资源和空间，并且改善Vt滚降。 氧化物材料也形成在掩埋位线上以改善（例如，增加）位线和字线之间的击穿电压，从而允许编程和擦除电荷之间的更大区分，并且更可靠的结果数据存储。 该方法还有助于减少掩埋位线宽度，从而允许位线更靠近地形成。 因此，更多的设备可以在相同或较小的区域内“打包”。

公开(公告)号：US06680509B1

公开(公告)日：2004-01-20

申请号：US10158044

申请日：2002-05-30

申请人： Yider Wu ,  Jean Yee-Mei Yang ,  Mark Ramsbey ,  Emmanuel H. Lingunis ,  Yu Sun

发明人： Yider Wu ,  Jean Yee-Mei Yang ,  Mark Ramsbey ,  Emmanuel H. Lingunis ,  Yu Sun

IPC分类号： H01L29792

CPC分类号： H01L27/11568 ,  H01L27/115 ,  Y10S438/954

摘要： A method for fabricating a SONOS device having a buried bit-line including the steps of: providing a semiconductor substrate having an ONO structure overlying the semiconductor substrate; forming a nitride barrier layer on the ONO structure to form, a four-layer stack; forming a patterned photoresist layer on the nitride barrier layer; implanting As or P ions through the four-layer stack to form a bit-line buried under the ONO structure; stripping the photoresist layer and cleaning an upper surface of the four-layer stack; and consolidating the four-layer stack by applying an oxidation cycle. The invention further relates to a SONOS-type device including the nitride barrier layer.

摘要翻译： 一种用于制造具有掩埋位线的SONOS器件的方法，包括以下步骤：提供具有覆盖在半导体衬底上的ONO结构的半导体衬底; 在ONO结构上形成氮化物阻挡层以形成四层堆叠; 在氮化物阻挡层上形成图案化的光致抗蚀剂层; 将As或P离子注入四层堆叠中以形成埋在ONO结构下的位线; 剥离光致抗蚀剂层并清洁四层堆叠的上表面; 并通过施加氧化循环来合并四层堆叠。 本发明还涉及包括氮化物阻挡层的SONOS型器件。

公开(公告)号：US06440797B1

公开(公告)日：2002-08-27

申请号：US09966702

申请日：2001-09-28

申请人： Yider Wu ,  Jean Yee-Mei Yang ,  Mark Ramsbey ,  Emmanuel H. Lingunis ,  Yu Sun

发明人： Yider Wu ,  Jean Yee-Mei Yang ,  Mark Ramsbey ,  Emmanuel H. Lingunis ,  Yu Sun

IPC分类号： H01L218247

CPC分类号： H01L27/11568 ,  H01L27/115 ,  Y10S438/954

摘要： A method for fabricating a SONOS device having a buried bit-line including the steps of: providing a semiconductor substrate having an ONO structure overlying the semiconductor substrate; forming a nitride barrier layer on the ONO structure to form a four-layer stack; forming a patterned photoresist layer on the nitride barrier layer; implanting As or P ions through the four-layer stack to form a bit-line buried under the ONO structure; stripping the photoresist layer and cleaning an upper surface of the four-layer stack; and consolidating the four-layer stack by applying an oxidation cycle. The invention further relates to a SONOS-type device including the nitride barrier layer.

摘要翻译： 一种用于制造具有掩埋位线的SONOS器件的方法，包括以下步骤：提供具有覆盖在半导体衬底上的ONO结构的半导体衬底; 在ONO结构上形成氮化物阻挡层以形成四层堆叠; 在所述氮化物阻挡层上形成图案化的光致抗蚀剂层; 将As或P离子注入四层堆叠中以形成埋在ONO结构下的位线; 剥离光致抗蚀剂层并清洁四层堆叠的上表面; 并通过施加氧化循环来合并四层堆叠。 本发明还涉及包括氮化物阻挡层的SONOS型器件。

公开(公告)号：US20050255651A1

公开(公告)日：2005-11-17

申请号：US10843289

申请日：2004-05-11

申请人： Weidong Qian ,  Mark Ramsbey ,  Jean-Yee-Mei Yang ,  Sameer Haddad

发明人： Weidong Qian ,  Mark Ramsbey ,  Jean-Yee-Mei Yang ,  Sameer Haddad

IPC分类号： H01L21/8246 ,  H01L27/115 ,  H01L21/4763

CPC分类号： H01L27/115 ,  H01L27/11568

摘要： The present invention pertains to implementing a dual poly process in forming a transistor based memory device. The process allows buried bitlines to be formed with less energy and to shallower depths than conventional bitlines to save resources and space, and to improve Vt roll-off. Oxide materials are also formed over the buried bitlines to improve (e.g., increase) a breakdown voltage between the bitlines and wordlines, thus allowing for greater discrimination between programming and erasing charges and more reliable resulting data storage. The process also facilitates a reduction in buried bitline width and thus allows bitlines to be formed closer together. As a result, more devices can be “packed” within the same or a smaller area.

摘要翻译： 本发明涉及在形成基于晶体管的存储器件中实现双重聚合工艺。 该过程允许以比常规位线更少的能量和更浅的深度形成掩埋位线，以节省资源和空间，并且改善Vt滚降。 氧化物材料也形成在掩埋位线上以改善（例如，增加）位线和字线之间的击穿电压，从而允许编程和擦除电荷之间的更大区分，并且更可靠的结果数据存储。 该方法还有助于减少掩埋位线宽度，从而允许位线更靠近地形成。 因此，更多的设备可以在相同或较小的区域内“打包”。

公开(公告)号：US07176113B1

公开(公告)日：2007-02-13

申请号：US10862636

申请日：2004-06-07

申请人： Nga-Ching Alan Wong ,  Weidong Qian ,  Sameer Haddad ,  Mark Randolph ,  Mark Ramsbey ,  Tazrien Kamal

发明人： Nga-Ching Alan Wong ,  Weidong Qian ,  Sameer Haddad ,  Mark Randolph ,  Mark Ramsbey ,  Tazrien Kamal

IPC分类号： H01L21/425

CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/7923

摘要： The present invention pertains to implementing a lightly doped channel (LDC) implant in fashioning a memory device to improve Vt roll-off, among other things. The lightly doped channel helps to preserve channel integrity such that a threshold voltage (Vt) can be maintained at a relatively stable level and thereby mitigate Vt roll-off. The LDC also facilitates a reduction in buried bitline width and thus allows the bitlines to be brought closer together. As a result more devices can be formed or “packed” within the same or a smaller area.

摘要翻译： 本发明涉及在形成存储器件中实施轻掺杂通道（LDC）植入物以改善Vt滚降等。 轻掺杂通道有助于保持通道完整性，使得阈值电压（Vt）可以保持在相对稳定的水平，从而减轻Vt滚降。 LDC还有助于减少掩埋位线宽度，从而使位线更靠近在一起。 因此，可以在相同或更小的区域内形成或“包装”更多的装置。

公开(公告)号：US07060554B2

公开(公告)日：2006-06-13

申请号：US10617451

申请日：2003-07-11

申请人： Minh Van Ngo ,  Mark Ramsbey ,  Tazrien Kamal ,  Pei Yuan Gao

发明人： Minh Van Ngo ,  Mark Ramsbey ,  Tazrien Kamal ,  Pei Yuan Gao

IPC分类号： H01L21/8242 ,  H01L21/336

CPC分类号： H01L27/11521 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/31604 ,  H01L21/76829 ,  H01L21/76834 ,  H01L23/552 ,  H01L27/115 ,  H01L29/66825 ,  H01L2924/0002 ,  H01L2924/00

摘要： A Si-rich silicon oxide layer having reduced UV transmission is deposited by PECVD, on an interlayer dielectric, prior to metallization, thereby reducing Vt. Embodiments include depositing a UV opaque Si-rich silicon oxide layer having an R.I. of 1.7 to 2.0.

摘要翻译： 在金属化之前，通过PECVD在层间电介质上沉积具有减少的UV透射的富Si氧化硅层，从而减少V O。 实施方案包括沉积具有1.7至2.0的R.I.的UV不透明的富Si氧化硅层。