公开(公告)号：US06917054B2

公开(公告)日：2005-07-12

申请号：US10681126

申请日：2003-10-09

申请人： Hidekatsu Onose ,  Hideo Homma ,  Atsuo Watanabe

发明人： Hidekatsu Onose ,  Hideo Homma ,  Atsuo Watanabe

IPC分类号： H01L29/80 ,  H01L21/337 ,  H01L29/10 ,  H01L29/772 ,  H01L29/808 ,  H01L31/0312 ,  H01L29/72

CPC分类号： H01L29/1066 ,  H01L29/1608 ,  H01L29/7722

摘要： A semiconductor device includes a trench formed on a source side of a drift region, a p-type gate region and a gate formed at the bottom of the trench, and the source formed over the entire surface of the unit device through an insulating film. The narrowest portion of a channel of the device is deeper than one-half the junction depth of the p-type gate region. This allows the width of the channel on the drain side to be reduced even when a lower energy ion implantation manufacturing process is used.

摘要翻译： 半导体器件包括形成在漂移区的源极侧的沟槽，形成在沟槽底部的p型栅极区域和栅极，并且源极通过绝缘膜形成在单元器件的整个表面上。 器件通道的最窄部分比p型栅极区域的结深的一半深。 这允许即使在使用较低能量的离子注入制造工艺时，漏极侧的沟道的宽度也被减小。

公开(公告)号：US06894346B2

公开(公告)日：2005-05-17

申请号：US10640411

申请日：2003-08-13

申请人： Hidekatsu Onose ,  Atsuo Watanabe

发明人： Hidekatsu Onose ,  Atsuo Watanabe

IPC分类号： H01L29/808 ,  H01L21/337 ,  H01L29/10 ,  H01L29/74 ,  H01L29/76 ,  H01L29/772 ,  H01L29/80 ,  H01L31/0256 ,  H01L30/0256

CPC分类号： H01L29/1066 ,  H01L29/7722 ,  H01L29/808

摘要： A structure is provided that ensures a low on-resistance and a better blocking effect. In a lateral type SIT (Static Induction Transistor) in which a first region is used as a p+ gate and a gate electrode is formed on the bottom of the first region, the structure is built such that the p+ gate and an n+ source are contiguous. An insulating film is formed on the surface of an n− channel, and an auxiliary gate electrode is formed on the insulating film. In addition, the auxiliary gate electrode and the source electrode are shorted.

摘要翻译： 提供了一种确保低导通电阻和更好的阻塞效果的结构。 在其中第一区被用作栅极的横向型SIT（静态感应晶体管）中，并且栅极电极形成在第一区域的底部上，构造为使得p ^{+ 门和n + 源是连续的。 在n通道的表面上形成绝缘膜，在绝缘膜上形成辅助栅电极。 此外，辅助栅电极和源电极短路。}

公开(公告)号：US07256453B2

公开(公告)日：2007-08-14

申请号：US11038929

申请日：2005-01-18

申请人： Hidekatsu Onose ,  Atsuo Watanabe

发明人： Hidekatsu Onose ,  Atsuo Watanabe

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： H01L29/1066 ,  H01L29/7722 ,  H01L29/808

摘要： A structure is provided that ensures a low on-resistance and a better blocking effect. In a lateral type SIT (Static Induction Transistor) in which a first region is used as a p+ gate and a gate electrode is formed on the bottom of the first region, the structure is built such that the p+ gate and an n+ source are contiguous. An insulating film is formed on the surface of an n− channel, and an auxiliary gate electrode is formed on the insulating film. In addition, the auxiliary gate electrode and the source electrode are shorted.

摘要翻译： 提供了一种确保低导通电阻和更好的阻塞效果的结构。 在其中第一区被用作栅极的横向型SIT（静态感应晶体管）中，并且栅极电极形成在第一区域的底部上，构造为使得p ^{+ 门和n + 源是连续的。 在n通道的表面上形成绝缘膜，在绝缘膜上形成辅助栅电极。 此外，辅助栅电极和源电极短路。}

公开(公告)号：US20050218424A1

公开(公告)日：2005-10-06

申请号：US11135417

申请日：2005-05-24

申请人： Hidekatsu Onose ,  Hideo Homma ,  Atsuo Watanabe

发明人： Hidekatsu Onose ,  Hideo Homma ,  Atsuo Watanabe

IPC分类号： H01L29/80 ,  H01L21/337 ,  H01L29/10 ,  H01L29/772 ,  H01L29/808 ,  H01L29/32

CPC分类号： H01L29/1066 ,  H01L29/1608 ,  H01L29/7722

摘要： A semiconductor switching device for an inverter includes a first conductivity type, low impurity concentration, semiconductor substrate having a band gap equal to or greater than 2.0 eV, a first conductivity type first region formed in a first plane of the substrate having a resistance lower than the substrate, a first electrode formed in another plane of the first region, a first conductivity type second region formed in a second plane of the substrate, and a second electrode formed on the second region. A trench is formed in the second plane, a control region is formed from a bottom of the trench into the substrate and a control electrode of a different conductivity type is formed on the control region. The second electrode is formed over the control electrode through an insulator film, and the control electrode is formed on the trench sidewalls so the control region contacts the second region.

摘要翻译： 用于逆变器的半导体开关器件包括第一导电类型，低杂质浓度，具有等于或大于2.0eV的带隙的半导体衬底，形成在衬底的第一平面中的电阻低于 所述基板，形成在所述第一区域的另一平面中的第一电极，形成在所述基板的第二平面中的第一导电类型的第二区域和形成在所述第二区域上的第二电极。 在第二平面中形成沟槽，控制区域从沟槽的底部形成到衬底中，并且在控制区域上形成不同导电类型的控制电极。 第二电极通过绝缘膜形成在控制电极上，并且控制电极形成在沟槽侧壁上，使得控制区域接触第二区域。

公开(公告)号：US20050121717A1

公开(公告)日：2005-06-09

申请号：US11038929

申请日：2005-01-18

申请人： Hidekatsu Onose ,  Atsuo Watanabe

发明人： Hidekatsu Onose ,  Atsuo Watanabe

IPC分类号： H01L29/808 ,  H01L21/337 ,  H01L29/10 ,  H01L29/74 ,  H01L29/76 ,  H01L29/772 ,  H01L29/80 ,  H01L31/0256

CPC分类号： H01L29/1066 ,  H01L29/7722 ,  H01L29/808

摘要： A structure is provided that ensures a low on-resistance and a better blocking effect. In a lateral type SIT (Static Induction Transistor) in which a first region is used as a p+ gate and a gate electrode is formed on the bottom of the first region, the structure is built such that the p+ gate and an n+ source are contiguous. An insulating film is formed on the surface of an n− channel, and an auxiliary gate electrode is formed on the insulating film. In addition, the auxiliary gate electrode and the source electrode are shorted.

公开(公告)号：US08134207B2

公开(公告)日：2012-03-13

申请号：US12028157

申请日：2008-02-08

申请人： Atsuo Watanabe

发明人： Atsuo Watanabe

IPC分类号： H01L29/66 ,  H01L27/12 ,  H01L29/786 ,  H01L21/02 ,  H01L21/70

CPC分类号： H01L27/1203 ,  H01L21/76283 ,  H01L21/76286 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41775 ,  H01L29/66325 ,  H01L29/66681 ,  H01L29/7394 ,  H01L29/7824

摘要： In a high breakdown voltage semiconductor element among elements integrated together on an SOI substrate in which its rated voltage is shared between an embedded oxide layer and a drain region formed by an element active layer, both high integration and high breakdown voltage are realized while also securing suitability for practical implementation and practical use. The high breakdown voltage is realized without hampering size reduction of the element by forming an electrically floating layer of a conductivity type opposite to that of the drain region at the surface of the drain region. Further, the thickness of the embedded oxide layer is reduced to a level suitable for the practical implementation and practical use by setting the thickness of the element active layer of the SOI substrate at 30 μm or more.

摘要翻译： 在集成在SOI衬底上的元件之间的高耐压电压半导体元件中，其中在由衬底的氧化物层和由元件有源层形成的漏极区域之间共享额定电压，实现高集成度和高​​击穿电压，同时还确保 适用于实际实施和实际应用。 通过在漏极区的表面形成与漏极区相反的导电类型的电浮置层，实现了高的击穿电压，而不会妨碍元件的尺寸减小。 此外，通过将SOI衬底的元件有源层的厚度设定为30μm以上，将嵌入氧化物层的厚度减小到适于实际实现和实际应用的水平。

公开(公告)号：US08081781B2

公开(公告)日：2011-12-20

申请号：US11814791

申请日：2006-02-23

申请人： Atsuo Watanabe

发明人： Atsuo Watanabe

IPC分类号： H02B1/00

CPC分类号： H04S5/02 ,  H03F3/181 ,  H03F3/217 ,  H03F3/68 ,  H03F2200/03

摘要： For achieving an audio reproduction with high sound quality, in a multi-channel A/V amplifier, front speakers are driven with a parallel-drive bi-amplifier arrangement upon stereo reproduction. In the case of the multi-channel reproduction mode, the switching circuit allows an output signal of each channel of the decoder to be sent to speakers via amplifiers for each channel in one-to-one correspondence. On the other hand, in the case of the 2-channel stereo reproduction mode, the switching circuit allows at least two amplifiers among the plurality of amplifiers to be connected in parallel between the output signal for each of the channels L and R of the decoder and the speakers for each of the channels L and R, and also allows the timing of the output signals of the respective amplifiers to be varied.

摘要翻译： 为了实现高音质的音频再现，在多声道A / V放大器中，在立体声再现时，前置扬声器由并行驱动双放大器布置驱动。 在多声道再现模式的情况下，切换电路允许解码器的每个声道的输出信号通过一个对应的每个声道的放大器发送到扬声器。 另一方面，在2声道立体声再现模式的情况下，切换电路允许多个放大器中的至少两个放大器并联连接在解码器的每个通道L和R的输出信号之间 以及每个通道L和R的扬声器，并且还允许各个放大器的输出信号的定时改变。

公开(公告)号：US20080153216A1

公开(公告)日：2008-06-26

申请号：US12071186

申请日：2008-02-19

申请人： Rajesh Kumar ,  Tsuyoshi Yamamoto ,  Hiroki Nakamura ,  Toshiyuki Morishita ,  Takasumi Ohyanagi ,  Atsuo Watanabe

发明人： Rajesh Kumar ,  Tsuyoshi Yamamoto ,  Hiroki Nakamura ,  Toshiyuki Morishita ,  Takasumi Ohyanagi ,  Atsuo Watanabe

IPC分类号： H01L21/82

CPC分类号： H01L29/1608 ,  H01L27/098 ,  H01L29/0619 ,  H01L29/66068 ,  H01L29/8083

摘要： A manufacturing method of a silicon carbide semiconductor device includes the steps of: preparing a semiconductor substrate including a silicon carbide substrate, a drift layer and a first semiconductor layer; forming a plurality of first trenches in a cell portion; forming a gate layer on an inner wall of each first trench by an epitaxial growth method; forming a first insulation film on the surface of the semiconductor substrate; forming a gate electrode on the first insulation film for connecting to the gate layer electrically; forming a source electrode on the first insulation film for connecting to the first semiconductor layer in the cell portion; and forming a drain electrode connected to the silicon carbide substrate electrically.

摘要翻译： 碳化硅半导体器件的制造方法包括以下步骤：制备包括碳化硅衬底，漂移层和第一半导体层的半导体衬底; 在单元部分中形成多个第一沟槽; 通过外延生长法在每个第一沟槽的内壁上形成栅极层; 在所述半导体衬底的表面上形成第一绝缘膜; 在所述第一绝缘膜上形成用于电连接到所述栅极层的栅电极; 在所述第一绝缘膜上形成用于连接到所述单元部分中的所述第一半导体层的源电极; 以及电连接到所述碳化硅衬底的漏电极。

公开(公告)号：US20070241338A1

公开(公告)日：2007-10-18

申请号：US11783611

申请日：2007-04-10

申请人： Tsuyoshi Yamamoto ,  Toshio Sakakibara ,  Hiroki Nakamura ,  Toshiyuki Morishita ,  Takasumi Ooyanagi ,  Atsuo Watanabe

发明人： Tsuyoshi Yamamoto ,  Toshio Sakakibara ,  Hiroki Nakamura ,  Toshiyuki Morishita ,  Takasumi Ooyanagi ,  Atsuo Watanabe

IPC分类号： H01L31/0312

CPC分类号： H01L29/1608 ,  H01L29/0843 ,  H01L29/1066 ,  H01L29/8083 ,  H01L29/872

摘要： A SiC semiconductor device includes: a SiC substrate having a drain layer, a drift layer and a source layer stacked in this order; multiple trenches penetrating the source layer and reaching the drift layer; a gate layer on a sidewall of each trench; an insulation film on the sidewall of each trench covering the gate layer; a source electrode on the source layer; and a diode portion in or under the trench contacting the drift layer to provide a diode. The drift layer between the gate layer on the sidewalls of adjacent two trenches provides a channel region. The diode portion is coupled with the source electrode, and insulated from the gate layer with the insulation film.

摘要翻译： SiC半导体器件包括：具有漏极层，漂移层和源极层的SiC衬底; 多个沟槽穿透源层并到达漂移层; 每个沟槽的侧壁上的栅极层; 覆盖所述栅极层的每个沟槽的侧壁上的绝缘膜; 源极上的源电极; 以及与沟槽接触的沟槽中或下方的二极管部分，以提供二极管。 相邻两个沟槽的侧壁上的栅极层之间的漂移层提供沟道区域。 二极管部分与源电极耦合，并与绝缘膜与栅极层绝缘。

公开(公告)号：US20070221924A1

公开(公告)日：2007-09-27

申请号：US11802810

申请日：2007-05-25

申请人： Takasumi Ohyanagi ,  Atsuo Watanabe ,  Rajesh Malhan ,  Tsuyoshi Yamamoto ,  Toshiyuki Morishita

发明人： Takasumi Ohyanagi ,  Atsuo Watanabe ,  Rajesh Malhan ,  Tsuyoshi Yamamoto ,  Toshiyuki Morishita

IPC分类号： H01L29/772

CPC分类号： H01L29/66416 ,  H01L29/1608 ,  H01L29/7722 ,  H01L29/8083

摘要： A silicon carbide semiconductor device such as JFET, SIT and the like is provided for accomplishing a reduction in on-resistance and high-speed switching operations. In the JFET or SIT which turns on/off a current with a depletion layer extending in a channel between a gate region formed along trench grooves, a gate contact layer and a gate electrode, which can be supplied with voltages from the outside, are formed on one surface of a semiconductor substrate or on the bottom of the trench groove. A metal conductor (virtual gate electrode) is formed in ohmic contact with a p++ contact layer of the gate region on the bottom of the trench grooves independently of the gate electrode. The virtual gate electrode is electrically isolated from the gate electrode and an external wire.

摘要翻译： 提供诸如JFET，SIT等的碳化硅半导体器件用于实现导通电阻和高速开关操作的降低。 在JFET或SIT中，形成在沿着沟槽形成的栅极区之间的沟道中延伸的耗尽层的电流，可以从外部供应电压的栅极接触层和栅极电极 在半导体衬底的一个表面上或在沟槽槽的底部。 金属导体（虚拟栅电极）与沟槽沟槽底部的栅极区域的p ++接触层独立于栅电极形成欧姆接触。 虚拟栅电极与栅极电极和外部电线电隔离。