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    VARIABLE RESISTANCE MEMORY DEVICE AND METHOD OF FORMING THE SAME
    2.
    发明申请
    VARIABLE RESISTANCE MEMORY DEVICE AND METHOD OF FORMING THE SAME 有权
    可变电阻记忆体装置及其形成方法

    公开(公告)号：US20110147692A1

    公开(公告)日：2011-06-23

    申请号：US12973124

    申请日：2010-12-20

    申请人： JEONGHEE PARK ,  Hideki Horii ,  Hyeyoung Park ,  Jin Ho Oh ,  Hyun-Suk Kwon

    发明人： JEONGHEE PARK ,  Hideki Horii ,  Hyeyoung Park ,  Jin Ho Oh ,  Hyun-Suk Kwon

    IPC分类号： H01L45/00

    CPC分类号： H01L45/16 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/1293 ,  H01L45/141 ,  H01L45/1683

    摘要： Provided are a variable resistance memory device and a method of forming the same. The variable resistance memory device may include a substrate, a plurality of bottom electrodes on the substrate, and a first interlayer insulating layer including a trench formed therein. The trench exposes the bottom electrodes and extends in a first direction. The variable resistance memory device further includes a top electrode provided on the first interlayer insulating layer and extending in a second direction crossing the first direction and a plurality of variable resistance patterns provided in the trench and having sidewalls aligned with a sidewall of the top electrode.

    摘要翻译： 提供了一种可变电阻存储器件及其形成方法。 可变电阻存储器件可以包括衬底，在衬底上的多个底部电极，以及包括形成在其中的沟槽的第一层间绝缘层。 沟槽露出底部电极并沿第一方向延伸。 可变电阻存储器件还包括设置在第一层间绝缘层上并沿与第一方向交叉的第二方向延伸的顶电极和设置在沟槽中并具有与顶电极的侧壁对准的侧壁的多个可变电阻图案。

    Methods for fabricating phase change memory devices
    3.
    发明授权
    Methods for fabricating phase change memory devices 有权
    制造相变存储器件的方法

    公开(公告)号：US08871559B2

    公开(公告)日：2014-10-28

    申请号：US13154631

    申请日：2011-06-07

    申请人： Hideki Horii ,  Hyun-Suk Kwon ,  Hyeyoung Park

    发明人： Hideki Horii ,  Hyun-Suk Kwon ,  Hyeyoung Park

    IPC分类号： H01L21/00 ,  H01L45/00 ,  H01L27/24

    CPC分类号： H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/126 ,  H01L45/141 ,  H01L45/144 ,  H01L45/1683 ,  H01L45/1691

    摘要： Provided is a method for fabricating a phase change memory device. The method includes forming a plurality of bottom electrodes on a substrate, forming a first mold layer on the substrate to extend in a first direction where the bottom electrodes are exposed, forming a second mold layer on the substrate, the second mold layer extending in a second direction orthogonal to the first direction to expose parts of the bottom electrodes, forming a phase change material layer on the first and second mold layers to be connected to parts of the bottom electrodes dividing the phase change material layer as a plurality of phase change layers respectively connected to the parts of the bottom electrodes and forming a plurality of top electrodes on the phase change layers.

    摘要翻译： 提供了一种制造相变存储器件的方法。 该方法包括在基板上形成多个底部电极，在基板上形成第一模具层，以在底部电极暴露的第一方向上延伸，在基板上形成第二模具层，第二模具层 与所述第一方向正交的第二方向以暴露所述底部电极的部分，在所述第一和第二模具层上形成相变材料层，以连接到将相变材料层划分为多个相变层的底部电极的部分 分别连接到底部电极的部分并在相变层上形成多个顶部电极。

    Probe card and test apparatus including the same
    4.
    发明授权
    Probe card and test apparatus including the same 有权
    探针卡和测试仪器包括它们

    公开(公告)号：US08581612B2

    公开(公告)日：2013-11-12

    申请号：US12817826

    申请日：2010-06-17

    申请人： Hideki Horii ,  Young-kuk Kim ,  Mi-lim Park

    发明人： Hideki Horii ,  Young-kuk Kim ,  Mi-lim Park

    IPC分类号： G01R31/20

    CPC分类号： G01R31/2889

    摘要： A probe card and a test apparatus including the probe card for improving test reliability. The probe card may include a first input terminal Microelectromechanical Systems (MEMS) switch that connects a first input terminal and a first input probe pin, wherein the first input terminal MEMS switch comprises a control portion that receives an operation signal and a connection portion that connects the first input terminal and the first input probe pin. The probe card may further include a first output terminal MEMS switch that connects a first output terminal and a first output probe pin, wherein the first output terminal MEMS switch comprises a control portion that receives the operation signal and a connection portion that connects the first output terminal and the first output probe pin.

    摘要翻译： 探针卡和测试装置，包括用于提高测试可靠性的探针卡。 探针卡可以包括连接第一输入端和第一输入探针的第一输入端微机电系统（MEMS）开关，其中第一输入端MEMS开关包括接收操作信号的控制部分和连接 第一输入端和第一输入探针。 探针卡还可以包括连接第一输出端和第一输出探针的第一输出端MEMS开关，其中第一输出端MEMS开关包括接收操作信号的控制部分和连接第一输出端 端子和第一个输出探针。

    Phase Changeable Memory Device Structures
    6.
    发明申请
    Phase Changeable Memory Device Structures 有权
    相变存储器件结构

    公开(公告)号：US20080272357A1

    公开(公告)日：2008-11-06

    申请号：US12132920

    申请日：2008-06-04

    申请人： Hideki Horii ,  Suk-Ho Joo ,  Ji-Hye Yi

    发明人： Hideki Horii ,  Suk-Ho Joo ,  Ji-Hye Yi

    IPC分类号： H01L47/00

    CPC分类号： H01L45/06 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1293 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1675

    摘要： A phase-changeable memory device may include a substrate, an insulating layer on the substrate, first and second electrodes, and a pattern of a phase-changeable material between the first and second electrodes. More particularly, the insulating layer may have a hole therein, and the first electrode may be in the hole in the insulating layer. Moreover, portions of the second electrode may extend beyond an edge of the pattern of phase-changeable material. Related methods are also discussed.

    摘要翻译： 可相变存储器件可以包括衬底，衬底上的绝缘层，第一和第二电极以及第一和第二电极之间的相变材料的图案。 更具体地，绝缘层可以在其中具有孔，并且第一电极可以在绝缘层中的孔中。 此外，第二电极的部分可以延伸超过相变材料图案的边缘。 还讨论了相关方法。

    Phase changeable memory cell array region and method of forming the same
    7.
    发明申请
    Phase changeable memory cell array region and method of forming the same 有权
    相变存储单元阵列区域及其形成方法

    公开(公告)号：US20070111440A1

    公开(公告)日：2007-05-17

    申请号：US11581012

    申请日：2006-10-16

    申请人： Hyeong-Geun An ,  Hideki Horii ,  Sang-Yeol Kang

    发明人： Hyeong-Geun An ,  Hideki Horii ,  Sang-Yeol Kang

    IPC分类号： H01L21/00 ,  H01L21/336 ,  H01L29/94

    CPC分类号： H01L45/144 ,  H01L27/2436 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1293 ,  H01L45/165 ,  H01L45/1666

    摘要： A phase changeable memory cell array region includes a lower interlayer insulating layer disposed on a semiconductor substrate. The region also includes a plurality of conductive plugs disposed through the lower interlayer insulating layer. The region also includes a phase changeable material pattern operably disposed on the lower interlayer insulating layer, the phase changeable pattern covering at least two of the plurality of conductive plugs, wherein the phase changeable material pattern includes a plurality of first regions in contact with one or more of the plurality of conductive plugs and at least one second region interposed between the plurality of the first regions, wherein the at least one second region has a lower thermal conductivity than the plurality of first regions. The phase changeable memory cell array region also includes an upper interlayer insulating layer covering at least one of the phase changeable material pattern and the lower interlayer insulating layer. The region also includes conductive patterns disposed through the upper interlayer insulating layer and electrically connected to a plurality of predetermined regions of the plurality of first regions.

    摘要翻译： 相变存储单元阵列区域包括设置在半导体衬底上的下层间绝缘层。 该区域还包括穿过下层间绝缘层设置的多个导电插塞。 所述区域还包括可操作地设置在所述下层间绝缘层上的可相变材料图案，所述相变图案覆盖所述多个导电插塞中的至少两个，其中所述相变材料图案包括多个与第 多个导电插塞中的多个和插入在多个第一区域之间的至少一个第二区域，其中至少一个第二区域具有比多个第一区域更低的热导率。 相变存储单元阵列区域还包括覆盖相变材料图案和下层间绝缘层中的至少一个的上层间绝缘层。 该区域还包括通过上层间绝缘层设置并电连接到多个第一区域中的多个预定区域的导电图案。

    Phase changeable memory devices having multi-level data storage elements and methods of fabricating the same
    9.
    发明授权
    Phase changeable memory devices having multi-level data storage elements and methods of fabricating the same 有权

    公开(公告)号：US07037762B2

    公开(公告)日：2006-05-02

    申请号：US10430980

    申请日：2003-05-07

    申请人： Jae-Hyun Joo ,  Hideki Horii

    发明人： Jae-Hyun Joo ,  Hideki Horii

    IPC分类号： H01L21/82

    CPC分类号： H01L27/2436 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

    摘要： A phase changeable memory device includes a lower interlayer dielectric layer on a semiconductor substrate. A plurality of first phase changeable data storage elements is disposed on the lower interlayer dielectric layer. A middle interlayer dielectric layer covers the first phase changeable data storage elements and the lower interlayer dielectric layer. A plurality of second phase changeable data storage elements is disposed on the middle interlayer dielectric layer. The first and second phase changeable data storage elements are arrayed in rows and columns such that respective first phase changeable data storage elements are disposed between respective adjacent second phase changeable data storage elements in the rows and columns. A plate electrode overlies the first and second phase changeable data storage elements and is electrically connected to the first and second phase changeable data storage elements. Related fabrication methods are also disclosed.

    Method of forming a conductive line for a semiconductor device using a carbon nanotube and semiconductor device manufactured using the method
    10.
    发明申请
    Method of forming a conductive line for a semiconductor device using a carbon nanotube and semiconductor device manufactured using the method 有权
    使用碳纳米管形成半导体器件导电线的方法和使用该方法制造的半导体器件

    公开(公告)号：US20060046445A1

    公开(公告)日：2006-03-02

    申请号：US11258037

    申请日：2005-10-26

    申请人： Won-bong Choi ,  Eun-ju Bae ,  Hideki Horii

    发明人： Won-bong Choi ,  Eun-ju Bae ,  Hideki Horii

    IPC分类号： H01L21/26 ,  H01L21/44

    CPC分类号： H01L21/28562 ,  B82Y10/00 ,  G11C13/025 ,  G11C2213/16 ,  H01L21/76879 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53276 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/16 ,  H01L2221/1094 ,  H01L2924/0002 ,  Y10S977/75 ,  H01L2924/00

    摘要： In a method of forming a conductive line for a semiconductor device using a carbon nanotube and a semiconductor device manufactured using the method, the method includes activating a surface of an electrode of the semiconductor device using surface pretreatment to create an activated surface of the electrode, forming an insulating layer on the activated surface of the electrode, and forming a contact hole through the insulating layer to expose a portion of the activated surface of the electrode, and supplying a carbon-containing gas onto the activated surface of the electrode through the contact hole to grow a carbon nanotube, which forms the conductive line, on the activated surface of the electrode. Alternatively, the activation step of the surface of the electrode may be replaced with a formation of a catalytic metal layer on the surface of the electrode.

    摘要翻译： 在使用碳纳米管制造的半导体器件的导线形成方法和使用该方法制造的半导体器件的方法中，该方法包括使用表面预处理来激活半导体器件的电极的表面以产生电极的活化表面， 在所述电极的活化表面上形成绝缘层，以及通过所述绝缘层形成接触孔以暴露所述电极的活化表面的一部分，并且通过所述触点将含碳气体供应到所述电极的活化表面上 孔，以在电极的活化表面上生长形成导电线的碳纳米管。 或者，可以在电极的表面上形成催化金属层来代替电极表面的活化步骤。