公开(公告)号：US06496886B1

公开(公告)日：2002-12-17

申请号：US09429441

申请日：1999-10-28

申请人： Hideki Osaka ,  Toyohiko Komatsu ,  Masahiro Kitano ,  Akira Yamagiwa ,  Ryoichi Kurihara

发明人： Hideki Osaka ,  Toyohiko Komatsu ,  Masahiro Kitano ,  Akira Yamagiwa ,  Ryoichi Kurihara

IPC分类号： H01P518

CPC分类号： H01P5/185 ,  H01P5/187 ,  H05K1/0228 ,  H05K1/023 ,  H05K1/0239 ,  H05K3/4623 ,  H05K2201/09236 ,  H05K2201/09845 ,  H05K2201/10689

摘要： In a printed board mounting method using a directional coupling bus for a high-speed data transfer, multi-bit data are transferred between nodes at a low cost. For this purpose, to transfer multi-bit data by directional coupling, a one-bit multi-coupling wiring network is vertically configured in a multilayered printed board. This minimizes the width of an area occupied by each bit along a wiring direction of the board to thereby implement a multi-bit configuration.

摘要翻译： 在使用用于高速数据传输的定向耦合总线的印刷电路板安装方法中，以比较低的成本在节点之间传送多位数据。 为此，为了通过定向耦合传输多位数据，在多层印刷电路板中垂直配置一位多耦合布线网络。 这使得沿着板的布线方向的每个位占据的面积的宽度最小化，从而实现多位配置。

公开(公告)号：US07515157B2

公开(公告)日：2009-04-07

申请号：US10333132

申请日：2000-12-14

申请人： Toyohiko Komatsu ,  Hideki Osaka ,  Masashi Horiguchi ,  Susumu Hatano ,  Kazuya Ito

发明人： Toyohiko Komatsu ,  Hideki Osaka ,  Masashi Horiguchi ,  Susumu Hatano ,  Kazuya Ito

IPC分类号： G06F13/14

CPC分类号： H04L12/40

摘要： A data transfer method is executed to transit a three-state transmitting circuit from a high-impedance state into a data output state, transmit a preamble (dummy data) onto a bus, and sequentially transmit the essential data. The shortening of a waveform caused in the first data piece after the transition from the high-impedance state into the data output state is executed against the preamble and no shortening of a waveform is not brought about in the essential data subsequent to the preamble. This makes it possible to exclude the limitation on speeding up the data transfer imposed by the shortening of the waveform.

摘要翻译： 执行数据传送方法以将三状态发送电路从高阻抗状态转移到数据输出状态，将前导码（虚拟数据）发送到总线上，并且顺序发送基本数据。 在从高阻抗状态转换到数据输出状态之后，在第一数据段中引起的波形的缩短针对前同步码执行，并且在前导码之后的基本数据中不会引起波形的缩短。 这使得可以排除由于缩短波形而加速数据传输的限制。

公开(公告)号：US06983023B2

公开(公告)日：2006-01-03

申请号：US09908710

申请日：2001-07-20

申请人： Hideki Osaka ,  Susumu Hatano ,  Toyohiko Komatsu ,  Tsutomu Hara

发明人： Hideki Osaka ,  Susumu Hatano ,  Toyohiko Komatsu ,  Tsutomu Hara

IPC分类号： H04B3/00

CPC分类号： H04L25/028 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/1084 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/15192 ,  H01L2924/15311 ,  H04B3/00 ,  H04L25/0266 ,  H04L25/0292 ,  H01L2924/00 ,  H01L2224/0401

摘要： A memory module bus system using a plurality of directional couplers to permit high-density packaging. A wiring line (main line) extending from a main controller and cooperating with a sub coupling line to form a directional coupler is open-ended or short-circuited to ensure that a forward wave and a reflection wave can be used to generate signals in opposite directions of the directional coupler. Memory modules are connected to opposite ends of the sub coupling line. The line length of the coupler can be half the pitch between the memory modules.

公开(公告)号：US06924651B2

公开(公告)日：2005-08-02

申请号：US10212209

申请日：2002-08-06

申请人： Hideki Osaka ,  Toyohiko Komatsu

发明人： Hideki Osaka ,  Toyohiko Komatsu

IPC分类号： G01R31/02 ,  G01R5/00 ,  G01R31/11 ,  G01R31/28 ,  G01R27/28 ,  G01R31/00

CPC分类号： G01R31/11 ,  G01R31/2806 ,  Y10T29/49004 ,  Y10T29/4913

摘要： A printed board inspecting apparatus includes: an input unit for inputting a pulse from a first signal line; a receiving unit for receiving a voltage induced in a second signal line in response to the input pulse inputted; and a judging unit for judging whether or not a ratio between a voltage of the input pulse and the voltage induced in the second signal line is within a predetermined range. A check is made using a TDR method to determine whether or not the degree of coupling is within a range of specified values and a check is made to determine each of the voltage of the polarized RZ signal and the pulse width time is within a range of specified values to thereby inspect a printed board and a semiconductor chip constituting a bus using a directional coupler.

摘要翻译： 印刷电路板检查装置包括：输入单元，用于输入来自第一信号线的脉冲; 接收单元，用于响应输入的输入脉冲接收在第二信号线中感应的电压; 以及判断单元，用于判断输入脉冲的电压与第二信号线中感应的电压之间的比率是否在预定范围内。 使用TDR方法进行检查，以确定耦合度是否在指定值的范围内，并且进行检查以确定极化RZ信号的每个电压，并且脉冲宽度时间在 从而使用定向耦合器检查构成总线的印刷电路板和半导体芯片。

公开(公告)号：US06829749B2

公开(公告)日：2004-12-07

申请号：US10214126

申请日：2002-08-08

申请人： Hideki Osaka ,  Toyohiko Komatsu

发明人： Hideki Osaka ,  Toyohiko Komatsu

IPC分类号： G06F1750

CPC分类号： H01P5/185 ,  G06F17/5036 ,  G06F17/5068 ,  H01P5/187 ,  H05K1/0239 ,  H05K3/0005

摘要： The number of steps for preparing a layout diagram of a circuit including a coupler, which is formed by arranging a main line and a stub line in parallel with each other, is reduced. A circuit diagram editor 1902 arranges a coupler symbol 100 stored in a component symbol storage section 1904 when the coupler is arranged in preparing a circuit diagram. A layout section 1935 of a layout diagram editor 1922 layouts two wirings constituting the coupler by use of circuit diagram information and coupler information in which a coupler length and a coupler interval are defined. An object extraction section 1937 of a wiring check section 1936 extracts components and wirings from the layout diagram, and passes these to a wiring checker 1938. At this time, the coupler is passed to the wiring checker as one component that cannot be decomposed no more. Therefore, an interval between two wirings constituting the coupler is not checked.

摘要翻译： 减少了通过将主线和短线布置成彼此平行而形成的包括耦合器的电路布局图的步骤数。 当制造电路图时，电路图编辑器1902布置存储在元件符号存储部分1904中的耦合器符号100。 布局图编辑器1922的布局部分1935通过使用其中限定了耦合器长度和耦合器间隔的电路图信息和耦合器信息来布置构成耦合器的两个布线。 布线检查部1936的物体提取部1937从布局图中提取部件和布线，并将其传递到布线检查器1938.此时，耦合器作为不能分解的一个部件被传递到布线检查器 。 因此，不检查构成耦合器的两条布线之间的间隔。

公开(公告)号：US06654270B2

公开(公告)日：2003-11-25

申请号：US10191112

申请日：2002-07-10

申请人： Hideki Osaka ,  Toyohiko Komatsu ,  Takashi Tsunehiro ,  Koichi Kimura ,  Susumu Hatano ,  Kazuya Ito ,  Toshio Sugano

发明人： Hideki Osaka ,  Toyohiko Komatsu ,  Takashi Tsunehiro ,  Koichi Kimura ,  Susumu Hatano ,  Kazuya Ito ,  Toshio Sugano

IPC分类号： G11C502

CPC分类号： G11C5/063 ,  G11C5/04

摘要： Conventionally, wiring length occupied by a directional coupler decides intervals between modules connected to a bus, and those intervals can not be shortened furthermore. Accordingly, the intervals between modules are wide and high-density mounting is not possible. In the present invention, a directional coupler in a memory bus is formed by a leader line from a controller and a leader line from a memory chip and contained within a memory module. Accordingly, pitch between the modules can be reduced and high-density mounting can be realized.

公开(公告)号：US07257725B2

公开(公告)日：2007-08-14

申请号：US10294594

申请日：2002-11-15

申请人： Hideki Osaka ,  Toyohiko Komatsu ,  Masashi Horiguchi ,  Susumu Hatano ,  Kazuya Ito

发明人： Hideki Osaka ,  Toyohiko Komatsu ,  Masashi Horiguchi ,  Susumu Hatano ,  Kazuya Ito

IPC分类号： G06F1/00

CPC分类号： G06F13/4086

摘要： A clock is located at a position close to a plurality of memory modules connected to a memory controller and located away from the controller, and wiring is carried out so that read access is preferential for transmission of read data. With respect to write data, a delay amount corresponding to a round-trip propagation delay time to each of the modules is measured and writing of the write data is carried out while maintaining a known time relationship between the clock and data. To measure round-trip reflection, lines are wired between the modules and a location detection circuit in a 1:1 relationship, and the circuit measures a time taken from a signal output time of a driver having the same impedance as that of the wired lines to a reflected-wave reception time of a hysteresis receiver.

摘要翻译： 时钟位于靠近与存储器控制器并且远离控制器的多个存储器模块的位置，并且执行布线，使得读取访问优先于读取数据的传输。 对于写数据，测量对应于每个模块的往返传播延迟时间的延迟量，并且在保持时钟和数据之间的已知时间关系的同时执行写入数据的写入。 为了测量往返反射，线路以1：1的关系连接到模块和位置检测电路之间，并且电路测量从具有与有线线路相同阻抗的驱动器的信号输出时间所花费的时间 到滞后接收器的反射波接收时间。

公开(公告)号：US06978328B1

公开(公告)日：2005-12-20

申请号：US09570349

申请日：2000-05-12

申请人： Hideki Osaka ,  Takashi Tsunehiro ,  Koichi Kimura ,  Susumu Hatano ,  Kazuya Ito ,  Toshio Sugano ,  Toyohiko Komatsu

发明人： Hideki Osaka ,  Takashi Tsunehiro ,  Koichi Kimura ,  Susumu Hatano ,  Kazuya Ito ,  Toshio Sugano ,  Toyohiko Komatsu

IPC分类号： G06F3/00 ,  G06F1/00 ,  G06F12/00 ,  G06F13/16 ,  H01P5/00 ,  H01P5/18 ,  H05K1/00 ,  H05K1/02 ,  H05K1/14

CPC分类号： H05K1/0246 ,  H05K1/0228 ,  H05K1/0298 ,  H05K1/14 ,  H05K2201/044 ,  H05K2201/09236 ,  H05K2201/09627 ,  H05K2201/10022

摘要： A bus system for carrying out data transfer between one bus master and a plurality of bus slaves. The bus system includes plural directional couplers which are formed by arranging respective parts of lines drawn from the bus slaves, without being in contact with, in the neighborhood of, and in parallel with a line drawn from the bus master. The line drawn from the bus master to a terminating resistance is wired to be folded. The directional couplers are further formed by arranging parts of the lines drawn from the bus slaves alternatively with respect to a first line part of the line drawn from the bus master ranging from the bus master to a fold of the line drawn from the bus master and with respect to a second line part of the line drawn from the bus master ranging from the fold to the terminating resistance.

摘要翻译： 一种用于在一个总线主机和多个总线从站之间执行数据传输的总线系统。 总线系统包括多个定向耦合器，其通过布置从总线从站引出的线的相应部分而形成，而不与从总线主控板引出的线相邻并且平行。 从总线主站到终端电阻的线被布线以折叠。 定向耦合器还通过将从总线主机引出的线路的一部分相对于从总线主机从总线主机抽出的线的第一线部分交替地排列成从总线主机引出的线的一部分， 相对于从总线主线抽出的从折叠到终止电阻的线的第二线部分。

公开(公告)号：US06438012B1

公开(公告)日：2002-08-20

申请号：US09569876

申请日：2000-05-12

申请人： Hideki Osaka ,  Toyohiko Komatsu ,  Takashi Tsunehiro ,  Koichi Kimura ,  Susumu Hatano ,  Kazuya Ito ,  Toshio Sugano

发明人： Hideki Osaka ,  Toyohiko Komatsu ,  Takashi Tsunehiro ,  Koichi Kimura ,  Susumu Hatano ,  Kazuya Ito ,  Toshio Sugano

IPC分类号： G11C800

CPC分类号： G11C5/063 ,  G11C5/04

摘要： Conventionally, wiring length occupied by a directional coupler decides intervals between modules connected to a bus, and those intervals can not be shortened furthermore. Accordingly, the intervals between modules are wide and high-density mounting is not possible. In the present invention, a directional coupler in a memory bus is formed by a leader line from a controller and a leader line from a memory chip and contained within a memory module. Accordingly, pitch between the modules can be reduced and high-density mounting can be realized.

摘要翻译： 常规地，由定向耦合器占用的布线长度决定了连接到总线的模块之间的间隔，并且这些间隔不能进一步缩短。 因此，模块之间的间隔宽，并且高密度安装是不可能的。 在本发明中，存储器总线中的定向耦合器由来自控制器的引线和来自存储器芯片的引出线形成并且包含在存储器模块中。 因此，可以减少模块之间的间距并实现高密度的安装。