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1.发明授权Video display apparatus with vertical scan velocity modulation and video display method thereof 失效具有垂直扫描速度调制的视频显示装置及其视频显示方法公开(公告)号：US06912015B1
公开(公告)日：2005-06-28
申请号：US09719397
申请日：1999-06-07
申请人： Hideyo Uwabata , Katsumi Terai , Minoru Miyata , Toshiaki Kitahara , Naoji Okumura , Kazuto Tanaka
发明人： Hideyo Uwabata , Katsumi Terai , Minoru Miyata , Toshiaki Kitahara , Naoji Okumura , Kazuto Tanaka
摘要： A parallel scanning circuit outputs a parallel scanning signal for making forward and backward scanning lines parallel. A vertical correlation detection circuit detects a portion where the change in luminance in the vertical direction exceeds a predetermined value on the basis of a luminance signal, and outputs a movement control signal representing the distance of movement on the screen of the scanning line. A retrace period reversion circuit reverses the lime axis of the movement control signal in a retrace period. A clamping circuit clamps the movement control signal to a predetermined DC voltage at the timing of horizontal synchronizing signal. A synthesizing circuit synthesizes the parallel scanning signal and the movement control signal, and feeds a synthesized signal as a vertical velocity modulation signal to a vertical velocity modulation coil.
摘要翻译： 并行扫描电路输出用于使前后扫描线平行的并行扫描信号。 垂直相关检测电路基于亮度信号检测垂直方向的亮度变化超过预定值的部分，并且在扫描线的屏幕上输出表示移动距离的移动控制信号。 回扫周期反转电路在回扫期间反转运动控制信号的石灰轴。 钳位电路在水平同步信号的定时将移动控制信号钳位到预定的DC电压。 合成电路合成并行扫描信号和移动控制信号，并将合成信号作为垂直速度调制信号馈送到垂直速度调制线圈。
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公开(公告)号：US06704056B2
公开(公告)日：2004-03-09
申请号：US09861587
申请日：2001-05-22
IPC分类号： H04N510
摘要： A video signal conversion part of a horizontal deflection circuit deletes a prescribed number of horizontal scanning lines from a vertical blanking interval of an input video signal and assigns a time corresponding to the deleted horizontal scanning lines to horizontal blanking intervals of the remaining horizontal scanning lines thereby extending the horizontal blanking interval of each horizontal scanning line and outputting a video signal. A synchronizing signal separation circuit extracts a horizontal synchronizing signal and a vertical synchronizing signal from the video signal output from the video signal conversion part. An output part of the horizontal deflection circuit supplies a sawtooth horizontal deflection current to a horizontal deflection yoke in synchronization with the horizontal synchronizing signal output from the synchronizing signal separation circuit.
摘要翻译： 水平偏转电路的视频信号转换部分从输入视频信号的垂直消隐间隔中删除规定数量的水平扫描线，并将与删除的水平扫描线对应的时间分配给其余水平扫描线的水平消隐间隔，由此 延长每条水平扫描线的水平消隐间隔并输出视频信号。 同步信号分离电路从视频信号转换部分输出的视频信号中提取水平同步信号和垂直同步信号。 水平偏转电路的输出部分与从同步信号分离电路输出的水平同步信号同步地向水平偏转线圈提供锯齿水平偏转电流。
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公开(公告)号：US5982449A
公开(公告)日：1999-11-09
申请号：US780253
申请日：1997-01-08
申请人： Miho Nagai , Takashi Yamaguchi , Yutaka Nio , Hideto Nakahigashi , Hideyo Uwabata , Toshiaki Kitahara , Chikara Gotanda , Atsushi Ishizu
发明人： Miho Nagai , Takashi Yamaguchi , Yutaka Nio , Hideto Nakahigashi , Hideyo Uwabata , Toshiaki Kitahara , Chikara Gotanda , Atsushi Ishizu
摘要： A television receiver comprising an information extracting circuit for extracting information from a format or content of an input video signal, a video signal processing circuit for processing this video signal by a program or data, a memory for storing the program and data, a CPU for controlling, operating or driving these elements, and a display device for displaying an image. The video signal processing circuit can, under the control of the CPU, decode the signal, correct or set the picture quality such as gradation and sharpness, or adaptively process an on-screen display based on the input video signal. The television receiver is also able to adaptively extend the functions of the television receiver corresponding to various signal formats.
摘要翻译： 一种电视接收机，包括：用于从输入视频信号的格式或内容中提取信息的信息提取电路，用于通过程序或数据处理该视频信号的视频信号处理电路，用于存储程序和数据的存储器，用于存储程序和数据的存储器 控制，操作或驱动这些元件，以及用于显示图像的显示装置。 视频信号处理电路可以在CPU的控制下对信号进行解码，校正或设置诸如灰度和清晰度的图像质量，或者基于输入视频信号自适应地处理屏幕显示。 电视接收机还能够自适应地扩展对应于各种信号格式的电视接收机的功能。
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4.发明授权Method for forming patterns on a semiconductor device using a lift off technique 失效使用剥离技术在半导体器件上形成图案的方法公开(公告)号：US07029938B2
公开(公告)日：2006-04-18
申请号：US10809525
申请日：2004-03-26
IPC分类号： H01L21/00 , H01L21/8238
CPC分类号： H01L29/66318 , H01L29/0657 , H01L29/41708 , H01L29/42304 , H01L29/7371
摘要： Upon formation of a collector electrode around a base mesa by the lift-off method, a resist film is formed over connection portions between the outer periphery of a region OA1 and a region in which the base mesa is formed, followed by successive formation of gold germanium, nickel and Au in this order over the entire surface of a substrate, so that the resulting stacked film will not become an isolated pattern. Thus, the stacked film over the base mesa is connected to a stacked film at the outer periphery of the region OA1, facilitating peeling of the stacked film over the base mesa. Generation of side etching upon formation of a via hole extending from the back side of the substrate to a backside via electrode is reduced by forming the backside via electrode using a material which hardly reacts with an n-type GaAs layer or n-type InGaAs layer.
摘要翻译： 通过剥离法在集电体周围形成集电体电极时，在区域OA1的外周与形成有基台面的区域之间的连接部分上形成抗蚀剂膜，接着形成 金，锗，金等，从而使得所得到的层叠膜不会成为隔离图案。 因此，基底台面上的层叠膜在区域OA1的外周与层叠膜连接，有利于层叠膜在基台面上的剥离。 通过使用几乎不与n型GaAs层或n型InGaAs层反应的材料形成背面通孔电极来减少形成从基板的背面延伸到背面通孔电极的通孔形成侧面蚀刻 。
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5.发明申请Method for forming patterns on a semiconductor device using a lift off technique 失效使用剥离技术在半导体器件上形成图案的方法公开(公告)号：US20060032762A1
公开(公告)日：2006-02-16
申请号：US11257060
申请日：2005-10-25
IPC分类号： B65D75/00
CPC分类号： H01L29/66318 , H01L29/0657 , H01L29/41708 , H01L29/42304 , H01L29/7371
摘要： Provided is a technique of improving the properties of a bipolar transistor. Described specifically, upon formation of a collector electrode around a base mesa by the lift-off method, a resist film is formed over connection portions between the outer periphery of a region OA1 and a region in which the base mesa 4a is formed, followed by successive formation of gold germanium (AuGe), nickel (Ni) and Au in the order of mention over the entire surface of a substrate so that the stacked film of them will not become an isolated pattern. As a result, the stacked film over the base mesa 4a is connected to a stacked film at the outer periphery of the region OA1, facilitating peeling of the stacked film over the base mesa 4a. In addition, generation of side etching upon formation of a via hole extending from the back side of the substrate to a backside via electrode is reduced by forming the backside via electrode using a material such as WSi which hardly reacts with an n type GaAs layer or n type InGaAs layer.
摘要翻译： 提供了改进双极晶体管的性质的技术。 具体地说，通过剥离法在基台周围形成集电极时，在区域OA1的外周与形成有基台面4a的区域之间的连接部分上形成抗蚀剂膜， 随后在衬底的整个表面上依次形成金锗（AuGe），镍（Ni）和Au，使得它们的堆叠膜不会变成隔离图案。 结果，基底台面4a上的层叠膜在区域OA1的外周与层叠膜连接，有利于层叠膜在基台面4a上的剥离。 此外，通过使用几乎不与n型GaAs层反应的诸如WSi的材料形成背面通孔电极来减少形成从基板的背面延伸到背面通孔电极的通孔形成侧面蚀刻，或 n型InGaAs层。
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公开(公告)号：US06867079B2
公开(公告)日：2005-03-15
申请号：US10673374
申请日：2003-09-30
IPC分类号： H01L29/872 , H01L21/3205 , H01L21/329 , H01L21/331 , H01L21/822 , H01L21/8222 , H01L23/52 , H01L27/04 , H01L27/06 , H01L29/47 , H01L29/737 , H01L21/338
CPC分类号： H01L29/66143 , H01L21/8252 , H01L27/0605 , H01L27/0652 , H01L27/0658 , H01L27/0664 , H01L29/475 , H01L29/66212 , H01L29/66318 , H01L29/7371
摘要： The present invention achieves the enhancement of a manufacturing yield factor and the reduction of manufacturing cost in a manufacturing method of a semiconductor device having a hetero junction bipolar transistor (HBT), a Schottky diode and a resistance element. The present invention is directed to the manufacturing method of a semiconductor device in which respective semiconductor layers which become a sub collector layer, a collector layer, a base layer, a wide gap emitter layer and an emitter layer are sequentially formed over one surface of a semiconductor substrate and, thereafter, respective semiconductor layers are processed to form the hetero junction bipolar transistor, the Schottky diode and the resistance element in a monolithic manner. An emitter electrode of the hetero junction bipolar transistor, a Schottky electrode of the Schottky diode and a resistance film of the resistance element are simultaneously formed using a same material (for example, WSiN). Accordingly, the man-hours can be reduced and the manufacturing cost of the semiconductor device can be reduced.
摘要翻译： 本发明在具有异质结双极晶体管（HBT），肖特基二极管和电阻元件的半导体器件的制造方法中实现了制造成品率的提高和制造成本的降低。 本发明涉及一种半导体器件的制造方法，其中，在半导体器件的一个表面上依次形成成为副集电极层，集电极层，基极层，宽间隙发射极层和发射极层的各个半导体层 半导体衬底，然后处理各个半导体层以形成异质结双极晶体管，肖特基二极管和电阻元件。 使用相同的材料（例如WSiN）同时形成异质结双极晶体管的发射极，肖特基二极管的肖特基电极和电阻元件的电阻膜。 因此，可以减少工时，并且可以降低半导体器件的制造成本。
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公开(公告)号：US07132320B2
公开(公告)日：2006-11-07
申请号：US11266259
申请日：2005-11-04
IPC分类号： H01L21/338
CPC分类号： H01L29/66143 , H01L21/8252 , H01L27/0605 , H01L27/0652 , H01L27/0658 , H01L27/0664 , H01L29/475 , H01L29/66212 , H01L29/66318 , H01L29/7371
摘要： The present invention achieves the enhancement of a manufacturing yield factor and the reduction of manufacturing cost in a manufacturing method of a semiconductor device having a hetero junction bipolar transistor (HBT), a Schottky diode and a resistance element. The present invention is directed to the manufacturing method of a semiconductor device in which respective semiconductor layers which become a sub collector layer, a collector layer, a base layer, a wide gap emitter layer and an emitter layer are sequentially formed over one surface of a semiconductor substrate and, thereafter, respective semiconductor layers are processed to form the hetero junction bipolar transistor, the Schottky diode and the resistance element in a monolithic manner. An emitter electrode of the hetero junction bipolar transistor, a Schottky electrode of the Schottky diode and a resistance film of the resistance element are simultaneously formed using a same material (for example, WSiN). Accordingly, the man-hours can be reduced and the manufacturing cost of the semiconductor device can be reduced.
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公开(公告)号：US06989301B2
公开(公告)日：2006-01-24
申请号：US10673217
申请日：2003-09-30
IPC分类号： H01L21/338
CPC分类号： H01L29/66143 , H01L21/8252 , H01L27/0605 , H01L27/0652 , H01L27/0658 , H01L27/0664 , H01L29/475 , H01L29/66212 , H01L29/66318 , H01L29/7371
摘要： The present invention achieves the enhancement of a manufacturing yield factor and the reduction of manufacturing cost in a manufacturing method of a semiconductor device having a hetero junction bipolar transistor (HBT), a Schottky diode and a resistance element. The present invention is directed to the manufacturing method of a semiconductor device in which respective semiconductor layers which become a sub collector layer, a collector layer, a base layer, a wide gap emitter layer and an emitter layer are sequentially formed over one surface of a semiconductor substrate and, thereafter, respective semiconductor layers are processed to form the hetero junction bipolar transistor, the Schottky diode and the resistance element in a monolithic manner. An emitter electrode of the hetero junction bipolar transistor, a Schottky electrode of the Schottky diode and a resistance film of the resistance element are simultaneously formed using a same material (for example, WSiN). Accordingly, the man-hours can be reduced and the manufacturing cost of the semiconductor device can be reduced.
摘要翻译： 本发明在具有异质结双极晶体管（HBT），肖特基二极管和电阻元件的半导体器件的制造方法中实现了制造成品率的提高和制造成本的降低。 本发明涉及一种半导体器件的制造方法，其中，在半导体器件的一个表面上依次形成成为副集电极层，集电极层，基极层，宽间隙发射极层和发射极层的各个半导体层 半导体衬底，然后处理各个半导体层以形成异质结双极晶体管，肖特基二极管和电阻元件。 使用相同的材料（例如WSiN）同时形成异质结双极晶体管的发射极，肖特基二极管的肖特基电极和电阻元件的电阻膜。 因此，可以减少工时，并且可以降低半导体器件的制造成本。
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公开(公告)号：US06441860B1
公开(公告)日：2002-08-27
申请号：US08852388
申请日：1997-05-07
申请人： Takashi Yamaguchi , Yutaka Nio , Toshiaki Kitahara
发明人： Takashi Yamaguchi , Yutaka Nio , Toshiaki Kitahara
IPC分类号： H04N701
CPC分类号： H04N5/46
摘要： A video signal processing apparatus which can process video signals with different formats simply by switching between programs for processing video signals. Different system clock signals are sent to the input and output processes by employing a programmable signal processor 4, input synchronizing signal processor 8, programmable signal processor 6 and output synchronizing pulse processor 9. A method for processing the video signal can be flexibly changed simply by switching between signal processing programs for programmable signal processors. In addition, the use of a memory 5 enables the signal, which is processed using the system clock signal in the input process, to be processed using the system clock signal in the output process. The present invention thus allows the processing of video signals with many different signal formats. The design of efficient circuitry will greatly reduce costs and production processes.
摘要翻译： 一种视频信号处理装置，其可以通过在用于处理视频信号的程序之间切换来处理具有不同格式的视频信号 通过采用可编程信号处理器4，输入同步信号处理器8，可编程信号处理器6和输出同步脉冲处理器9，将不同的系统时钟信号发送到输入和输出处理。用于处理视频信号的方法可以简单地通过 在可编程信号处理器的信号处理程序之间切换。 此外，使用存储器5使得能够使用输出处理中的系统时钟信号来处理在输入处理中使用系统时钟信号处理的信号。 因此，本发明允许处理具有许多不同信号格式的视频信号。 高效电路的设计将大大降低成本和生产流程。
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10.发明授权Method for forming patterns on a semiconductor device using a lift off technique 失效使用剥离技术在半导体器件上形成图案的方法公开(公告)号：US07214558B2
公开(公告)日：2007-05-08
申请号：US11257060
申请日：2005-10-25
IPC分类号： H01L21/00 , H01L21/8235
CPC分类号： H01L29/66318 , H01L29/0657 , H01L29/41708 , H01L29/42304 , H01L29/7371
摘要： Provided is a technique of improving the properties of a bipolar transistor. Described specifically, upon formation of a collector electrode around a base mesa by the lift-off method, a resist film is formed over connection portions between the outer periphery of a region OA1 and a region in which the base mesa 4a is formed, followed by successive formation of gold germanium (AuGe), nickel (Ni) and Au in the order of mention over the entire surface of a substrate so that the stacked film of them will not become an isolated pattern. As a result, the stacked film over the base mesa 4a is connected to a stacked film at the outer periphery of the region OA1, facilitating peeling of the stacked film over the base mesa 4a. In addition, generation of side etching upon formation of a via hole extending from the back side of the substrate to a backside via electrode is reduced by forming the backside via electrode using a material such as WSi which hardly reacts with an n type GaAs layer or n type InGaAs layer.
摘要翻译： 提供了改进双极晶体管的性质的技术。 具体地说，通过剥离法在基台周围形成集电极时，在区域OA1的外周与形成有基台面4a的区域之间的连接部分上形成抗蚀剂膜， 随后在衬底的整个表面上依次形成金锗（AuGe），镍（Ni）和Au，使得它们的堆叠膜不会变成隔离图案。 结果，基底台面4a上的层叠膜在区域OA1的外周与层叠膜连接，有利于层叠膜在基台面4a上的剥离。 此外，通过使用几乎不与n型GaAs层反应的诸如WSi的材料形成背面通孔电极来减少形成从基板的背面延伸到背面通孔电极的通孔形成侧面蚀刻，或 n型InGaAs层。
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