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    Method for fabricating semiconductor device using a CVD insulator film
    2.
    发明授权
    Method for fabricating semiconductor device using a CVD insulator film 有权
    使用CVD绝缘膜制造半导体器件的方法

    公开(公告)号：US06472281B2

    公开(公告)日：2002-10-29

    申请号：US09238584

    申请日：1999-01-28

    申请人： Hiroyuki Doi ,  Yasushi Okuda ,  Keita Takahashi ,  Nobuyuki Tamura

    发明人： Hiroyuki Doi ,  Yasushi Okuda ,  Keita Takahashi ,  Nobuyuki Tamura

    IPC分类号： H01L21336

    CPC分类号： H01L29/66825 ,  H01L21/2652 ,  H01L21/28273 ,  H01L21/31612 ,  H01L29/6656 ,  H01L29/6659

    摘要： A gate insulator film and a gate electrode are formed on an Si substrate, and a CVD insulator film is deposited thereon to cover the gate electrode. Then, arsenic ions are implanted into the Si substrate from above the CVD insulator film to form LDD layers. After sidewall spacers have been formed over the side faces of the gate electrode with the CVD insulator film interposed therebetween, source/drain layers are formed. Since the LDD layers are formed by implanting dopant ions through the CVD insulator film, the passage of arsenic ions through the ends of the gate electrode can be suppressed. As a result, a semiconductor device suitable for miniaturization can be formed, while suppressing deterioration in insulating properties of the gate oxide film due to the passage of dopant ions through the ends of the gate electrode.

    摘要翻译： 在Si衬底上形成栅极绝缘体膜和栅电极，并在其上沉积CVD绝缘膜以覆盖栅电极。 然后，从CVD绝缘膜上方将砷离子注入Si衬底中以形成LDD层。 在栅电极的侧面上形成有侧壁间隔物之后，CVD绝缘体膜之间形成有源极/漏极层。 由于通过CVD绝缘膜注入掺杂剂离子形成LDD层，因此能够抑制砷离子通过栅电极的端部。 结果，可以形成适合于小型化的半导体器件，同时抑制由于掺杂剂离子通过栅电极的端部而导致的栅极氧化膜的绝缘性能的劣化。

    Method of manufacturing semiconductor device
    3.
    发明授权
    Method of manufacturing semiconductor device 失效
    制造半导体器件的方法

    公开(公告)号：US06753222B2

    公开(公告)日：2004-06-22

    申请号：US10271879

    申请日：2002-10-15

    申请人： Ken Mimuro ,  Hiroyuki Doi ,  Yasushi Okuda

    发明人： Ken Mimuro ,  Hiroyuki Doi ,  Yasushi Okuda

    IPC分类号： H01L21336

    CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11534

    摘要： A method for forming a semiconductor device is provided that allows a desirable semiconductor device to be obtained by preventing a gate electrode of a non-volatile semiconductor memory from having an abnormal shape and the surfaces of high concentration source and drain regions of the non-volatile semiconductor memory from being worn away. The method includes a first step of forming a non-volatile semiconductor memory in a first region of a substrate of the semiconductor device and a second step of forming a semiconductor device in a second region on the substrate. The non-volatile semiconductor memory includes a first gate including a tunnel insulating film, a floating gate electrode, a capacitor insulating film, and a control gate electrode, and the semiconductor device includes a second gate including a gate insulating film and a gate electrode. In this method, during patterning of the second gate, a surface of the first gate is covered with a protective film that hardly can be etched by an etchant used for the patterning of the second gate.

    摘要翻译： 提供一种用于形成半导体器件的方法，其通过防止非易失性半导体存储器的栅电极具有异常形状并且使非挥发性的高浓度源极和漏极区域的表面能够获得期望的半导体器件 半导体存储器被磨损掉。 该方法包括在半导体器件的衬底的第一区域中形成非易失性半导体存储器的第一步骤和在衬底上的第二区域中形成半导体器件的第二步骤。 非易失性半导体存储器包括：第一栅极，其包括隧道绝缘膜，浮栅电极，电容绝缘膜和控制栅电极，并且所述半导体器件包括包括栅极绝缘膜和栅电极的第二栅极。 在该方法中，在图案化第二栅极期间，第一栅极的表面被几乎不能被用于第二栅极图案化的蚀刻剂所蚀刻的保护膜覆盖。

    Non-volatile semiconductor memory having a ring-shaped floating gate
    4.
    发明授权
    Non-volatile semiconductor memory having a ring-shaped floating gate 失效
    具有环形浮动栅极的非易失性半导体存储器

    公开(公告)号：US5510639A

    公开(公告)日：1996-04-23

    申请号：US384791

    申请日：1995-02-09

    申请人： Yasushi Okuda ,  Yoshinori Odake ,  Ichiro Nakao ,  Youhei Ichikawa

    发明人： Yasushi Okuda ,  Yoshinori Odake ,  Ichiro Nakao ,  Youhei Ichikawa

    IPC分类号： H01L21/336 ,  H01L27/115 ,  H01L29/06 ,  H01L29/788 ,  H01L29/76

    CPC分类号： H01L29/66825 ,  H01L27/115 ,  H01L29/0692 ,  H01L29/7885

    摘要： A non-volatile semiconductor memory cell having a novel structure is provided. The memory cell has a ring-shaped channel region formed on a semiconductor substrate, a drain region formed in a zone surrounded by the channel region, and a source region formed outside the channel region. The cell further includes a first gate insulation layer formed on the substrate in such a manner as to cover the boundary between the channel region and the drain region, a ring-shaped floating gate electrode formed on the first gate insulation layer, a second gate insulation layer formed on the floating gate electrode; and a control gate electrode which is capacitive-coupled with the floating gate via the second gate insulation layer.

    摘要翻译： 提供具有新颖结构的非易失性半导体存储单元。 存储单元具有形成在半导体衬底上的环形沟道区域，形成在由沟道区域包围的区域中的漏极区域和形成在沟道区域外部的源极区域。 电池还包括以覆盖沟道区域和漏极区域之间的边界的方式形成在衬底上的第一栅极绝缘层，形成在第一栅极绝缘层上的环形浮栅电极，第二栅极绝缘层 形成在浮栅电极上的层; 以及通过第二栅极绝缘层与浮动栅极电容耦合的控制栅电极。

    Ink composition
    5.
    发明授权
    Ink composition 失效
    墨水组成

    公开(公告)号：US4657591A

    公开(公告)日：1987-04-14

    申请号：US590913

    申请日：1984-03-15

    申请人： Keiko Shioi ,  Yasushi Okuda

    发明人： Keiko Shioi ,  Yasushi Okuda

    IPC分类号： C09D11/00 ,  B65H54/02 ,  B65H54/70 ,  B65H67/056 ,  C09D11/10 ,  C09D11/16

    CPC分类号： C09D11/17

    摘要： An ink composition for writing on an absorbent or pervious writing surface to form thereon a writing or marking composed of an inner portion of a metallic color with outer contour portions therearound of a dyestuff-based color, which composition comprises:a nonleafing metal powder pigment as a first pigment,an inorganic or organic pigment as a second pigment,a dyestuff, anda solvent,the nonleafing metal powder pigment being dispersed in the solvent and having a particle size sufficiently large so as to substantially not permeate or be absorbed into the writing surface, andthe second pigment being dispersed in the solvent and either having a particle size sufficiently large so as to substantially not permeate or be absorbed into the writing surface, or having a particle size sufficiently large so as to substantially be adsorbed on the nonleafing metal powder pigment,the dyestuff being dissolved in the solvent, being capable of substantially permeating or being absorbed into the writing surface and diffusing into the area on the writing surface proximate to the writing,whereby the nonleafing metal powder pigment forms in conjunction with the second pigment the inner portion of the metallic color, and the dyestuff forms the outer contour portions of the dyestuff-based color around the inner portion.

    摘要翻译： 一种用于在吸收性或可渗透的书写表面上书写的油墨组合物，以在其上形成由金属颜色的内部部分组成的书写或标记，其中包含基于染料的颜色的外部轮廓部分，该组合物包括：非底漆金属粉末颜料 第一颜料，作为第二颜料的无机或有机颜料，染料和溶剂，非漂洗性金属粉末颜料分散在溶剂中并且具有足够大的粒径，以便基本上不渗透或被吸收到书写中 表面，并且第二颜料分散在溶剂中，并且具有足够大的粒度，以便基本上不渗透或被吸收到书写表面，或者具有足够大的粒度以便基本上被吸附在非擦洗金属上 粉末颜料，染料溶于溶剂中，能够基本渗透或吸收到w中 在书写表面附近扩散到书写表面上的区域，由此非擦洗金属粉末颜料与第二颜料一起形成金属颜色的内部，染料形成基于染料的外部轮廓部分 颜色围绕内部。

    Nonvolatile semiconductor memory device and method for driving the same
    6.
    发明授权
    Nonvolatile semiconductor memory device and method for driving the same 有权

    公开(公告)号：US06657893B2

    公开(公告)日：2003-12-02

    申请号：US10050965

    申请日：2002-01-22

    申请人： Keita Takahashi ,  Masafumi Doi ,  Hiroyuki Doi ,  Nobuyuki Tamura ,  Yasushi Okuda

    发明人： Keita Takahashi ,  Masafumi Doi ,  Hiroyuki Doi ,  Nobuyuki Tamura ,  Yasushi Okuda

    IPC分类号： G11C1604

    CPC分类号： G11C16/0416 ,  G11C16/0433 ,  H01L27/115

    摘要： A memory transistor and a select transistor are disposed side by side on a semiconductor substrate between source/drain diffusion layers thereof, with an intermediate diffusion layer interposed therebetween. The memory transistor includes: a gate insulating film having such a thickness as to allow tunneling current to pass therethrough; a floating gate electrode; an interelectrode insulating film; and a control gate electrode. The select transistor includes a gate insulating film and a select gate electrode. Tunneling current, allowing electrons to pass through the gate insulating film under the floating gate electrode, is utilized during the removal and injection of electrons from/into the floating gate electrode. As a result, higher reliability can be attained and rewriting can be performed at a lower voltage. Also, since the select transistor is provided, reading can also be performed at a lower voltage. Improvement of reliability and rewrite and read operations at respective lower voltages are realized for a nonvolatile semiconductor memory device, in which a memory cell includes a floating gate electrode and a control gate electrode.

    Nonvolatile semiconductor memory device and method for driving the same
    8.
    发明授权
    Nonvolatile semiconductor memory device and method for driving the same 失效
    非易失性半导体存储器件及其驱动方法

    公开(公告)号：US06377490B1

    公开(公告)日：2002-04-23

    申请号：US09677844

    申请日：2000-10-03

    申请人： Keita Takahashi ,  Masafumi Doi ,  Hiroyuki Doi ,  Nobuyuki Tamura ,  Yasushi Okuda

    发明人： Keita Takahashi ,  Masafumi Doi ,  Hiroyuki Doi ,  Nobuyuki Tamura ,  Yasushi Okuda

    IPC分类号： G11C1604

    CPC分类号： G11C16/0416 ,  G11C16/0433 ,  H01L27/115

    摘要： A memory transistor and a select transistor are disposed side by side on a semiconductor substrate between source/drain diffusion layers thereof, with an intermediate diffusion layer interposed therebetween. The memory transistor includes: a gate insulating film having such a thickness as to allow tunneling current to pass therethrough; a floating gate electrode; an interelectrode insulating film; and a control gate electrode. The select transistor includes a gate insulating film and a select gate electrode. Tunneling current, allowing electrons to pass through the gate insulating film under the floating gate electrode, is utilized during the removal and injection of electrons from/into the floating gate electrode. As a result, higher reliability can be attained and rewriting can be performed at a lower volt age. Also, since the select transistor is provided, reading c an also be performed at a lower voltage. Improvement of reliability and rewrite and read operations at respective lower voltages are realized for a nonvolatile semiconductor memory device, in which a memory cell includes a floating gate electrode and a control gate electrode.

    摘要翻译： 存储晶体管和选择晶体管并排地设置在其源极/漏极扩散层之间的半导体衬底上，介于其间的中间扩散层。 存储晶体管包括：栅极绝缘膜，具有允许隧穿电流通过的厚度; 浮栅电极; 电极间绝缘膜; 和控制栅电极。 选择晶体管包括栅极绝缘膜和选择栅电极。 在从浮栅电极移入和注入电子期间，利用允许电子通过浮栅电极下的栅极绝缘膜的隧穿电流。 结果，可以获得更高的可靠性并且可以在较低的电压时间进行重写。 此外，由于提供了选择晶体管，因此也可以在较低的电压下进行读取。 对于其中存储单元包括浮置栅电极和控制栅电极的非易失性半导体存储器件，实现了在各自的较低电压下的可靠性的改善和重写和读取操作。

    Method for driving a non-volatile semiconductor memory
    10.
    发明授权
    Method for driving a non-volatile semiconductor memory 失效
    用于驱动非易失性半导体存储器的方法

    公开(公告)号：US5715196A

    公开(公告)日：1998-02-03

    申请号：US684178

    申请日：1996-07-19

    申请人： Yoshinori Odake ,  Akira Asai ,  Yasushi Okuda ,  Toshiki Mori ,  Ichirou Nakao

    发明人： Yoshinori Odake ,  Akira Asai ,  Yasushi Okuda ,  Toshiki Mori ,  Ichirou Nakao

    IPC分类号： G11C16/04 ,  G11C16/26 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788

    CPC分类号： H01L27/11521 ,  G11C16/0416 ,  G11C16/26 ,  H01L27/115 ,  H01L29/66825 ,  H01L29/7883

    摘要： An array of non-volatile memory cells arranged in rows and columns is provided. Each memory cell is composed of a transistor made up of a gate, a source, and drain and a capacitance section. Each memory cell is connected to a row decoder through a wordline, to a column decoder through a bitline, and to a source decoder through a sourceline. Arranged in a path extending from a bitline to a sourceline through a transistor is an anisotropic resistance section, e.g., a diode, exhibiting different voltage-current characteristics for different levels of voltages applied thereacross. Because of such arrangement, leakage current occurring to a deselected memory cell in a reading operation can be reduced or can be eliminated. Read errors due to leakage current can be avoided and the power consumption can be reduced.

    摘要翻译： 提供了排列成行和列的非易失性存储单元阵列。 每个存储单元由由栅极，源极和漏极以及电容部分构成的晶体管构成。 每个存储单元通过字线连接到行解码器，通过位线连接到列解码器，并通过源线连接到源解码器。 在从位线延伸到源极线通过晶体管的路径中布置的是各向异性电阻部分，例如二极管，对于施加在其上的不同电压电平，具有不同的电压 - 电流特性。 由于这样的布置，可以减少或可以消除在读取操作中对取消选择的存储单元发生的泄漏电流。 可以避免由于泄漏电流而导致的读取错误，并且可以降低功耗。