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    SEMICONDUCTOR INTEGRATED CIRCUIT
    1.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
    半导体集成电路

    公开(公告)号：US20090045480A1

    公开(公告)日：2009-02-19

    申请号：US12094499

    申请日：2006-11-07

    申请人： Hiroki Matsunaga ,  Naoki Hishikawa ,  Akihiro Maejima ,  Jinsaku Kaneda ,  Hiroshi Ando

    发明人： Hiroki Matsunaga ,  Naoki Hishikawa ,  Akihiro Maejima ,  Jinsaku Kaneda ,  Hiroshi Ando

    IPC分类号： H01L27/02

    CPC分类号： H01L27/0207 ,  H01L27/12

    摘要： A semiconductor integrated circuit includes a plurality of circuit cells on a semiconductor chip. The plurality of circuit cells are formed along a first chip side of the semiconductor chip. Each of the plurality of circuit cells has a pad. The semiconductor integrated circuit further includes a high voltage potential interconnect formed over the plurality of circuit cells. The high voltage potential interconnect has a width expanding in a length direction from a center portion to end portions of the high voltage potential interconnect.

    摘要翻译： 半导体集成电路包括半导体芯片上的多个电路单元。 多个电路单元沿半导体芯片的第一芯片侧形成。 多个电路单元中的每一个具有衬垫。 半导体集成电路还包括形成在多个电路单元上的高压电位互连。 高压电位互连具有从高压电位互连的中心部分到端部的长度方向上的宽度。

    Driver circuit
    3.
    发明授权
    Driver circuit 有权
    驱动电路

    公开(公告)号：US07323923B2

    公开(公告)日：2008-01-29

    申请号：US11211638

    申请日：2005-08-26

    申请人： Eisaku Maeda ,  Hiroshi Ando ,  Jinsaku Kaneda ,  Akihiro Maejima ,  Hiroki Matsunaga

    发明人： Eisaku Maeda ,  Hiroshi Ando ,  Jinsaku Kaneda ,  Akihiro Maejima ,  Hiroki Matsunaga

    IPC分类号： H03L5/00

    CPC分类号： H03K3/356113 ,  G09G3/296 ,  G09G2330/04 ,  H03K3/012 ,  H03K19/0013

    摘要： A driver circuit is provided for preventing generation of a pass-through current in a CMOS output unit even if a power supply voltage VDD supplied from a low voltage power supply drops below a recommended operating power supply voltage. The driver circuit includes a level shift unit having PMOS transistors and NMOS transistors, and a CMOS output unit having a PMOS transistor and an NMOS transistor. The source, drain and gate of one PMOS transistor are respectively connected to a high voltage power supply, a first contact and a second contact. The source, drain and gate of a second PMOS transistor are respectively connected to a high voltage power supply, the second contact and the first contact. The source of one NMOS transistor is grounded, the drain thereof is connected to the first contact, and the gate thereof receives a low voltage signal. The source of a second NMOS transistor is grounded, the drain thereof is connected to the second contact, and the gate thereof receives a low voltage signal. In this driver circuit, the driving current of the one PMOS transistor is higher than the driving current of the one NMOS transistor.

    摘要翻译： 即使从低电压电源提供的电源电压VDD低于推荐的工作电源电压，也提供用于防止在CMOS输出单元中产生通过电流的驱动电路。 驱动器电路包括具有PMOS晶体管和NMOS晶体管的电平移位单元和具有PMOS晶体管和NMOS晶体管的CMOS输出单元。 一个PMOS晶体管的源极，漏极和栅极分别连接到高压电源，第一触点和第二触点。 第二PMOS晶体管的源极，漏极和栅极分别连接到高压电源，第二触点和第一触点。 一个NMOS晶体管的源极接地，其漏极连接到第一触点，其栅极接收低电压信号。 第二NMOS晶体管的源极接地，其漏极连接到第二触点，并且其栅极接收低电压信号。 在该驱动电路中，一个PMOS晶体管的驱动电流高于一个NMOS晶体管的驱动电流。

    Sustain driver, sustain control system, and display device
    5.
    发明授权
    Sustain driver, sustain control system, and display device 有权
    维持驱动器，维持控制系统和显示设备

    公开(公告)号：US07969429B2

    公开(公告)日：2011-06-28

    申请号：US11941240

    申请日：2007-11-16

    申请人： Masahiko Sasada ,  Hiroki Matsunaga ,  Masashi Inao ,  Hiroshi Ando ,  Jinsaku Kaneda ,  Eisaku Maeda ,  Akihiro Maejima

    发明人： Masahiko Sasada ,  Hiroki Matsunaga ,  Masashi Inao ,  Hiroshi Ando ,  Jinsaku Kaneda ,  Eisaku Maeda ,  Akihiro Maejima

    IPC分类号： H01L29/739 ,  H01L31/00 ,  H03F3/16 ,  G09G3/28 ,  G09G5/00 ,  G06F3/038 ,  H01L27/10 ,  H01L29/73 ,  H03F3/04 ,  G09G3/20

    CPC分类号： G09G3/296 ,  G09G3/282 ,  G09G3/294 ,  G09G2300/0408 ,  G09G2310/0289 ,  G09G2330/04

    摘要： The collector, emitter, and base of a bipolar transistor circuit are connected to a high side power supply terminal, the drain of a level shift transistor, and a floating power supply terminal, respectively. When a high side output transistor is on, the floating power supply terminal is at the potential of a high potential power supply terminal. The high side power supply terminal is at a potential higher than the potential of the floating power supply terminal by a constant voltage. Turning the level shift transistor on, its drain potential drops below the potential of the floating power supply terminal; The base current flows through the bipolar transistor circuit and the drain potential of the level shift transistor is clamped near the potential of the floating power supply terminal; The bipolar transistor circuit is turned on and its collector current supplies the drain current of the level shift transistor.

    摘要翻译： 双极晶体管电路的集电极，发射极和基极分别连接到高侧电源端子，电平移位晶体管的漏极和浮动电源端子。 当高边输出晶体管导通时，浮动电源端子处于高电位电源端子的电位。 高侧电源端子通过恒定电压处于高于浮动电源端子的电位的电位。 开启电平移位晶体管时，其漏极电位降低到浮动电源端子的电位以下; 基极电流流过双极晶体管电路，电平移位晶体管的漏极电压钳位在浮动电源端子的电位附近; 双极晶体管电路导通，其集电极电流提供电平移位晶体管的漏极电流。

    Circuit for generating ternary signal
    7.
    发明授权
    Circuit for generating ternary signal 失效
    用于产生三态信号的电路

    公开(公告)号：US07469016B2

    公开(公告)日：2008-12-23

    申请号：US11290062

    申请日：2005-11-30

    申请人： Jinsaku Kaneda ,  Akihiro Maejima ,  Hiroki Matsunaga ,  Eisaku Maeda ,  Hiroshi Ando

    发明人： Jinsaku Kaneda ,  Akihiro Maejima ,  Hiroki Matsunaga ,  Eisaku Maeda ,  Hiroshi Ando

    IPC分类号： H04L25/34

    CPC分类号： H03K3/00 ,  H03K17/00 ,  H03K17/693

    摘要： A circuit for generating a ternary signal that receives a binary input-control signal and a binary reset signal and outputs a ternary signal. The circuit includes first to third transistors, each source terminal thereof is respectively connected to the three power supplies, and a sequential circuit that outputs control signals controlling the transistors. The sequential circuit outputs control signals that make the first and the third transistors be switched in a complementary manner in an initial state, and make the second and the third transistors be switched in a state that it is released from the initial state.

    摘要翻译： 用于产生接收二进制输入控制信号和二进制复位信号并输出​​三进制信号的三态信号的电路。 电路包括第一至第三晶体管，其每个源极分别连接到三个电源，以及输出控制晶体管的控制信号的顺序电路。 顺序电路输出使得第一和第三晶体管在初始状态下以互补方式切换的控制信号，并且使第二和第三晶体管在从初始状态释放的状态下被切换。

    Sustain driver, sustain control system, and plasma display
    8.
    发明授权
    Sustain driver, sustain control system, and plasma display 有权
    维持驱动器，维持控制系统和等离子显示器

    公开(公告)号：US07358968B2

    公开(公告)日：2008-04-15

    申请号：US10991243

    申请日：2004-11-17

    申请人： Masahiko Sasada ,  Hiroki Matsunaga ,  Masashi Inao ,  Hiroshi Ando ,  Jinsaku Kaneda ,  Eisaku Maeda ,  Akihiro Maejima

    发明人： Masahiko Sasada ,  Hiroki Matsunaga ,  Masashi Inao ,  Hiroshi Ando ,  Jinsaku Kaneda ,  Eisaku Maeda ,  Akihiro Maejima

    IPC分类号： H01L29/739 ,  H01L31/00 ,  H03F3/16 ,  G09G3/28 ,  G09G5/00 ,  G06F3/038 ,  H01L27/10 ,  H01L29/73 ,  H03F3/04 ,  G09G3/20

    CPC分类号： G09G3/296 ,  G09G3/282 ,  G09G3/294 ,  G09G2300/0408 ,  G09G2310/0289 ,  G09G2330/04

    摘要： The collector, emitter, and base of a bipolar transistor circuit are connected to a high side power supply terminal, the drain of a level shift transistor, and a floating power supply terminal, respectively. When a high side output transistor is on, the floating power supply terminal is at the potential of a high potential power supply terminal. The high side power supply terminal is at a potential higher than the potential of the floating power supply terminal by a constant voltage. Turning the level shift transistor on, its drain potential drops below the potential of the floating power supply terminal; The base current flows through the bipolar transistor circuit and the drain potential of the level shift transistor is clamped near the potential of the floating power supply terminal; The bipolar transistor circuit is turned on and its collector current supplies the drain current of the level shift transistor.

    摘要翻译： 双极晶体管电路的集电极，发射极和基极分别连接到高侧电源端子，电平移位晶体管的漏极和浮动电源端子。 当高边输出晶体管导通时，浮动电源端子处于高电位电源端子的电位。 高侧电源端子通过恒定电压处于高于浮动电源端子的电位的电位。 开启电平移位晶体管时，其漏极电位降低到浮动电源端子的电位以下; 基极电流流过双极晶体管电路，电平移位晶体管的漏极电压钳位在浮动电源端子的电位附近; 双极晶体管电路导通，其集电极电流提供电平移位晶体管的漏极电流。

    Circuit for generating ternary signal
    9.
    发明申请
    Circuit for generating ternary signal 失效
    用于产生三态信号的电路

    公开(公告)号：US20060119389A1

    公开(公告)日：2006-06-08

    申请号：US11290062

    申请日：2005-11-30

    申请人： Jinsaku Kaneda ,  Akihiro Maejima ,  Hiroki Matsunaga ,  Eisaku Maeda ,  Hiroshi Ando

    发明人： Jinsaku Kaneda ,  Akihiro Maejima ,  Hiroki Matsunaga ,  Eisaku Maeda ,  Hiroshi Ando

    IPC分类号： H03K19/00

    CPC分类号： H03K3/00 ,  H03K17/00 ,  H03K17/693

    摘要： A circuit for generating a ternary signal that receives a binary input-control signal and a binary reset signal and outputs a ternary signal. The circuit includes first to third transistors, each source terminal thereof is respectively connected to the three power supplies, and a sequential circuit that outputs control signals controlling the transistors. The sequential circuit outputs control signals that make the first and the third transistors be switched in a complementary manner in an initial state, and make the second and the third transistors be switched in a state that it is released from the initial state.

    摘要翻译： 用于产生接收二进制输入控制信号和二进制复位信号并输出​​三进制信号的三态信号的电路。 电路包括第一至第三晶体管，其每个源极分别连接到三个电源，以及输出控制晶体管的控制信号的顺序电路。 顺序电路输出使得第一和第三晶体管在初始状态下以互补方式切换的控制信号，并且使第二和第三晶体管在从初始状态释放的状态下被切换。