公开(公告)号：US08399309B2

公开(公告)日：2013-03-19

申请号：US13109660

申请日：2011-05-17

申请人： Masaaki Ogino ,  Hiroki Wakimoto ,  Masayuki Miyazaki

发明人： Masaaki Ogino ,  Hiroki Wakimoto ,  Masayuki Miyazaki

IPC分类号： H01L21/00

CPC分类号： H01L29/66333 ,  H01L29/045 ,  H01L29/0657

摘要： A manufacturing method is disclosed which ensures strength of a wafer and improves device performance. A thermal diffusion layer is formed from a front surface of a wafer. A tapered groove which reaches the thermal diffusion layer is formed from a back surface by anisotropic etching with alkaline solution. In-groove thermal diffusion layer is formed on side wall surfaces of the groove. A separation layer of a reverse blocking IGBT is configured of the thermal diffusion layer and the in-groove diffusion layer. The thermal diffusion layer is formed shallowly by forming the in-groove diffusion layer. It is possible to considerably reduce thermal diffusion time. By carrying out an ion implantation forming the in-groove diffusion layer and an ion implantation forming a collector layer separately, it is possible to select an optimum value for tradeoff between turn-on voltage and switching loss, while ensuring reverse blocking voltage of the reverse blocking IGBT.

摘要翻译： 公开了一种确保晶片强度并提高器件性能的制造方法。 热扩散层由晶片的前表面形成。 通过各向异性蚀刻用碱性溶液从后表面形成到达热扩散层的锥形槽。 槽内热扩散层形成在槽的侧壁面上。 反向阻断IGBT的分离层由热扩散层和内槽扩散层构成。 通过形成内槽扩散层来形成浅扩散层。 可以显着地减少热扩散时间。 通过进行形成槽内扩散层的离子注入和分离形成集电极的离子注入，可以选择用于折合导通电压和开关损耗之间的最优值，同时确保反向的反向阻断电压 阻断IGBT。

公开(公告)号：US08604584B2

公开(公告)日：2013-12-10

申请号：US13038349

申请日：2011-03-01

申请人： Hiroki Wakimoto ,  Kenichi Iguchi ,  Koh Yoshikawa ,  Tsunehiro Nakajima ,  Shunsuke Tanaka ,  Masaaki Ogino

发明人： Hiroki Wakimoto ,  Kenichi Iguchi ,  Koh Yoshikawa ,  Tsunehiro Nakajima ,  Shunsuke Tanaka ,  Masaaki Ogino

IPC分类号： H01L21/78 ,  H01L21/302

CPC分类号： H01L21/308 ,  H01L21/302 ,  H01L21/78 ,  H01L29/06

摘要： Some embodiments of the present invention relate to a semiconductor device and a method of manufacturing a semiconductor device capable of preventing the deterioration of electrical characteristics. A p-type collector region is provided on a surface layer of a backside surface of an n-type drift region. A p+-type isolation layer for obtaining reverse blocking capability is provided at the end of an element. In addition, a concave portion is provided so as to extend from the backside surface of the n-type drift region to the p+-type isolation layer. A p-type region is provided and is electrically connected to the p+-type isolation layer. The p+-type isolation layer is provided so as to include a cleavage plane having the boundary between the bottom and the side wall of the concave portion as one side.

摘要翻译： 本发明的一些实施例涉及能够防止电特性劣化的半导体器件和半导体器件的制造方法。 p型集电极区域设置在n型漂移区域的背面的表面层上。 在元件的末端提供了用于获得反向阻挡能力的p +型隔离层。 此外，设置从n型漂移区的背面向p +型隔离层延伸的凹部。 提供p型区域并且电连接到p +型隔离层。 提供p +型隔离层，以便包括具有作为一侧的凹部的底部和侧壁之间的边界的解理面。

公开(公告)号：US09240456B2

公开(公告)日：2016-01-19

申请号：US14233147

申请日：2011-07-15

申请人： Hiroki Wakimoto ,  Masaaki Ogino

发明人： Hiroki Wakimoto ,  Masaaki Ogino

IPC分类号： H01L21/332 ,  H01L29/66 ,  H01L21/761 ,  H01L21/78 ,  H01L21/308 ,  H01L29/06

CPC分类号： H01L29/66325 ,  H01L21/3083 ,  H01L21/761 ,  H01L21/78 ,  H01L29/0619 ,  H01L29/0646 ,  H01L29/0661 ,  H01L29/66333

摘要： A method includes forming on a first main surface of a semiconductor wafer of a first conduction type, a gate electrode of a semiconductor element, an edge termination region for forming a breakdown voltage of the semiconductor element, and a first semiconductor region of a second conduction type which surrounds the semiconductor element and the edge termination region. A groove may be formed to reach the first semiconductor region from a second main surface of the semiconductor wafer. The groove is formed so that a portion of the semiconductor wafer, that forms an outer circumferential end of the semiconductor wafer, remains and the groove is further towards a center of the semiconductor wafer than the outer circumferential end. A third semiconductor region of the second conduction type is on a side wall of the groove and electrically connects the first semiconductor region and a second semiconductor region.

摘要翻译： 一种方法包括在第一导电类型的半导体晶片的第一主表面，半导体元件的栅电极，用于形成半导体元件的击穿电压的边缘终端区域和第二导电的第一半导体区域 围绕半导体元件和边缘终止区域的类型。 可以形成沟槽，以从半导体晶片的第二主表面到达第一半导体区域。 形成凹槽，使得形成半导体晶片的外周端的半导体晶片的一部分保留，并且凹槽比外周端更向着半导体晶片的中心。 第二导电类型的第三半导体区域位于沟槽的侧壁上，并电连接第一半导体区域和第二半导体区域。

公开(公告)号：US20140162413A1

公开(公告)日：2014-06-12

申请号：US14233147

申请日：2011-07-15

申请人： Hiroki Wakimoto ,  Masaaki Ogino

发明人： Hiroki Wakimoto ,  Masaaki Ogino

IPC分类号： H01L29/66

CPC分类号： H01L29/66325 ,  H01L21/3083 ,  H01L21/761 ,  H01L21/78 ,  H01L29/0619 ,  H01L29/0646 ,  H01L29/0661 ,  H01L29/66333

摘要： A method includes forming on a first main surface of a semiconductor wafer of a first conduction type, a gate electrode of a semiconductor element, an edge termination region for forming a breakdown voltage of the semiconductor element, and a first semiconductor region of a second conduction type which surrounds the semiconductor element and the edge termination region. A groove may be formed to reach the first semiconductor region from a second main surface of the semiconductor wafer. The groove is formed so that a portion of the semiconductor wafer, that forms an outer circumferential end of the semiconductor wafer, remains and the groove is further towards a center of the semiconductor wafer than the outer circumferential end. A third semiconductor region of the second conduction type is on a side wall of the groove and electrically connects the first semiconductor region and a second semiconductor region.

摘要翻译： 一种方法包括在第一导电类型的半导体晶片的第一主表面，半导体元件的栅电极，用于形成半导体元件的击穿电压的边缘终端区域和第二导电的第一半导体区域 围绕半导体元件和边缘终止区域的类型。 可以形成沟槽，以从半导体晶片的第二主表面到达第一半导体区域。 形成凹槽，使得形成半导体晶片的外周端的半导体晶片的一部分保留，并且凹槽比外周端更向着半导体晶片的中心。 第二导电类型的第三半导体区域位于沟槽的侧壁上，并电连接第一半导体区域和第二半导体区域。

公开(公告)号：US08008734B2

公开(公告)日：2011-08-30

申请号：US11972932

申请日：2008-01-11

申请人： Hiroki Wakimoto ,  Masahito Otsuki ,  Takashi Shiigi

发明人： Hiroki Wakimoto ,  Masahito Otsuki ,  Takashi Shiigi

IPC分类号： H01L29/66

CPC分类号： H01L29/7811 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/402 ,  H01L29/404 ,  H01L29/66734 ,  H01L29/7813

摘要： A power semiconductor device is provided having a field plate that employs a thick metal film in an edge termination structure and which permits edge termination structure width reduction even with large side etching or etching variation, which exhibits superior long-term forward blocking voltage capability reliability, and which allows minimal forward blocking voltage capability variation. The edge termination structure has multiple ring-like p-type guard rings, a first insulating film covering the guard rings, and ring-like field plates, provided via the first insulating film atop the guard rings. The field plates have a polysilicon film and a thicker metal film. The polysilicon film is provided on a first guard ring via first insulating film, and a dual field plate made of the polysilicon film and metal film is provided on a second guard ring. The dual field plate is stacked via a second insulating film. The first and second guard rings alternate.

摘要翻译： 提供了一种功率半导体器件，其具有采用边缘端接结构中的厚金属膜的场板，即使具有优异的长期正向阻断电压能力可靠性的大的侧蚀刻或蚀刻变化也允许边缘终端结构宽度减小， 并且其允许最小的正向阻断电压能力变化。 边缘端接结构具有多个环状p型保护环，覆盖保护环的第一绝缘膜和通过护罩顶部上的第一绝缘膜提供的环状场板。 场板具有多晶硅膜和较厚的金属膜。 多晶硅膜通过第一绝缘膜设置在第一保护环上，并且由多晶硅膜和金属膜制成的双场板设置在第二保护环上。 双场板通过第二绝缘膜堆叠。 第一和第二保卫环交替出现。

公开(公告)号：US20070252195A1

公开(公告)日：2007-11-01

申请号：US11741015

申请日：2007-04-27

申请人： Koh Yoshikawa ,  Hiroki Wakimoto ,  Masahito Otsuki

发明人： Koh Yoshikawa ,  Hiroki Wakimoto ,  Masahito Otsuki

IPC分类号： H01L31/00

CPC分类号： H01L29/7397 ,  H01L29/0696 ,  H01L29/66348

摘要： A vertical and trench type insulated gate MOS semiconductor device is provided in which the surfaces of p-type channel regions and the surfaces of portions of an n-type semiconductor substrate alternate in the longitudinal direction of the trench between the trenches arranged in parallel, and an n+-type emitter region selectively formed on the surface of the p-type channel region is wide by the side of the trench and becomes narrow toward the center point between the trenches. This enables the device to achieve low on-resistance and enhanced turn-off capability.

摘要翻译： 提供一种垂直和沟槽型绝缘栅极MOS半导体器件，其中p型沟道区域的表面和n型半导体衬底的部分表面在沟槽纵向方向上交替排列成平行布置，并且 选择性地形成在p型沟道区域的表面上的n + + +型发射极区域在沟槽侧面较宽，并且朝向沟槽之间的中心点变窄。 这使得器件能够实现低导通电阻和增强的关断能力。

公开(公告)号：US20070004098A1

公开(公告)日：2007-01-04

申请号：US11454121

申请日：2006-06-16

申请人： Kenichi Kazama ,  Tsunehiro Nakajima ,  Koji Sasaki ,  Akio Shimizu ,  Takashi Hayashi ,  Hiroki Wakimoto

发明人： Kenichi Kazama ,  Tsunehiro Nakajima ,  Koji Sasaki ,  Akio Shimizu ,  Takashi Hayashi ,  Hiroki Wakimoto

IPC分类号： H01L21/20

CPC分类号： H01L29/7393 ,  H01L29/0834 ,  H01L29/41725 ,  H01L29/456 ,  H01L29/66333 ,  H01L29/7395

摘要： A method of producing a semiconductor device having a thickness of 90 μm to 200 μm and with an electrode on the rear surface, which achieves a high proportion of non-defective devices by optimizing the silicon concentration and thickness of the aluminum-silicon electrode. A surface device structure is formed on a first major surface of a silicon substrate. A buffer layer and a collector layer are formed on the second major surface after grinding to reduce the thickness of the substrate. On the collector layer, a collector electrode is formed including a first layer of an aluminum-silicon film having a thickness of 0.3 μm to 1.0 μm and a silicon concentration of 0.5 percent to 2 percent by weight, preferably not more than 1 percent by weight.

摘要翻译： 一种制造厚度为90μm至200μm的半导体器件的方法，并且在后表面上具有电极，其通过优化铝硅电极的硅浓度和厚度来实现高比例的无缺陷器件。 在硅衬底的第一主表面上形成表面器件结构。 在研磨后的第二主表面上形成缓冲层和集电体层，以减小基板的厚度。 在集电体层上形成集电极，其包括厚度为0.3〜1.0μm的硅铝膜的第1层，硅浓度为0.5〜2重量％，优选为1重量％以下 。

公开(公告)号：US08531007B2

公开(公告)日：2013-09-10

申请号：US12784162

申请日：2010-05-20

申请人： Katsuya Okumura ,  Hiroki Wakimoto ,  Kazuo Shimoyama ,  Tomoyuki Yamazaki

发明人： Katsuya Okumura ,  Hiroki Wakimoto ,  Kazuo Shimoyama ,  Tomoyuki Yamazaki

IPC分类号： H01L29/06 ,  H01L21/302

CPC分类号： H01L29/0661 ,  H01L21/76224 ,  H01L29/0619 ,  H01L29/0657 ,  H01L29/0696 ,  H01L29/402 ,  H01L29/66333 ,  H01L29/7395

摘要： A semiconductor device is disclosed which includes active section 100, edge termination section 110 having a voltage blocking structure and disposed around active section 100, and separation section 120 having a device separation structure and disposed around edge termination section 110. A surface device structure is formed on the first major surface of active section 100, trench 23 is formed in separation section 120 from the second major surface side, and p+-type separation region 24 is formed on the side wall of trench 23 such that p+-type separation region 24 is in contact with p-type channel stopper region 21 formed in the surface portion on the first major surface side and p-type collector layer 9 formed in the surface portion on the second major surface side. The semiconductor device and the method for manufacturing the semiconductor device according to the invention facilitate preventing the reverse blocking voltage from decreasing and shorten the manufacturing time of the semiconductor device.

摘要翻译： 公开了一种半导体器件，其包括有源部分100，具有电压阻挡结构并设置在有源部分100周围的边缘终端部分110以及具有设备分离结构并且设置在边缘终端部分110周围的分离部分120.形成表面器件结构 在有源部分100的第一主表面上，在分离部分120中形成沟槽23与第二主表面侧，并且在沟槽23的侧壁上形成p +型分离区域24，使得p +型分离区域24为 与形成在第一主表面侧的表面部分中的p型沟道停止区域21和形成在第二主表面侧的表面部分中的p型集电极层9接触。 根据本发明的半导体器件和制造半导体器件的方法有助于防止反向阻断电压降低并缩短半导体器件的制造时间。

公开(公告)号：US08242556B2

公开(公告)日：2012-08-14

申请号：US12767356

申请日：2010-04-26

申请人： Koh Yoshikawa ,  Hiroki Wakimoto ,  Masahito Otsuki

发明人： Koh Yoshikawa ,  Hiroki Wakimoto ,  Masahito Otsuki

IPC分类号： H01L29/76

CPC分类号： H01L29/7397 ,  H01L29/0696 ,  H01L29/66348

摘要： A vertical and trench type insulated gate MOS semiconductor device is provided in which the surfaces of p-type channel regions and the surfaces of portions of an n-type semiconductor substrate alternate in the longitudinal direction of the trench between the trenches arranged in parallel, and an n+-type emitter region selectively formed on the surface of the p-type channel region is wide by the side of the trench and becomes narrow toward the center point between the trenches. This enables the device to achieve low on-resistance and enhanced turn-off capability.

摘要翻译： 提供一种垂直和沟槽型绝缘栅极MOS半导体器件，其中p型沟道区域的表面和n型半导体衬底的部分表面在沟槽纵向方向上交替排列成平行布置，并且 选择性地形成在p型沟道区域的表面上的n +型发射极区域在沟槽侧面较宽，并且朝向沟槽之间的中心点变窄。 这使得器件能够实现低导通电阻和增强的关断能力。

公开(公告)号：US07897452B2

公开(公告)日：2011-03-01

申请号：US11454121

申请日：2006-06-16

申请人： Kenichi Kazama ,  Tsunehiro Nakajima ,  Koji Sasaki ,  Akio Shimizu ,  Takashi Hayashi ,  Hiroki Wakimoto

发明人： Kenichi Kazama ,  Tsunehiro Nakajima ,  Koji Sasaki ,  Akio Shimizu ,  Takashi Hayashi ,  Hiroki Wakimoto

IPC分类号： H01L21/8249

CPC分类号： H01L29/7393 ,  H01L29/0834 ,  H01L29/41725 ,  H01L29/456 ,  H01L29/66333 ,  H01L29/7395

摘要： A method of producing a semiconductor device having a thickness of 90 μm to 200 μm and with an electrode on the rear surface, which achieves a high proportion of non-defective devices by optimizing the silicon concentration and thickness of the aluminum-silicon electrode. A surface device structure is formed on a first major surface of a silicon substrate. A buffer layer and a collector layer are formed on the second major surface after grinding to reduce the thickness of the substrate. On the collector layer, a collector electrode is formed including a first layer of an aluminum-silicon film having a thickness of 0.3 μm to 1.0 μm and a silicon concentration of 0.5 percent to 2 percent by weight, preferably not more than 1 percent by weight.

摘要翻译： 一种制造厚度为90μm至200μm的半导体器件的方法，并且在后表面上具有电极，通过优化硅 - 硅电极的硅浓度和厚度来实现高比例的无缺陷器件。 在硅衬底的第一主表面上形成表面器件结构。 在研磨后的第二主表面上形成缓冲层和集电体层，以减小基板的厚度。 在集电体层上形成集电极，其包括厚度为0.3〜1.0μm的硅铝膜的第一层，硅浓度为0.5〜2重量％，优选为1重量％以下 。