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1.发明授权Data transmission system capable of transmitting interrupt signal without interrupt gate period 有权数据传输系统能够在不中断门限周期的情况下传输中断信号公开(公告)号：US08548069B2
公开(公告)日：2013-10-01
申请号：US13142655
申请日：2010-10-13
申请人： Hiroshi Suenaga , Osamu Shibata , Yoshiyuki Saito , Kohei Masuda , Yoshihide Komatsu , Masashi Suzuki
发明人： Hiroshi Suenaga , Osamu Shibata , Yoshiyuki Saito , Kohei Masuda , Yoshihide Komatsu , Masashi Suzuki
IPC分类号： H04B3/00
CPC分类号： H04L25/0278
摘要： A data transmission system comprises: a pair of transmission lines connecting a plurality of apparatuses; a bridge termination resistor connected between the transmission lines and having a resistance value matching a differential impedance of the transmission lines; a first switch connecting the bridge termination resistor to the transmission lines when being turned on, and disconnecting the bridge termination resistor from the transmission lines when being turned off; pull-up/down resistors connected between the transmission lines and a fixed voltage node, and having resistance values respectively matching characteristic impedances of the transmission lines, the fixed voltage node being a power supply or a ground; and second switches connecting the pull-up/down resistors between the transmission lines and the fixed voltage node when being turned on, and disconnecting the pull-up/down resistors from the transmission lines when being turned off.
摘要翻译： 数据传输系统包括：一对连接多个设备的传输线; 连接在传输线之间并具有与传输线的差分阻抗匹配的电阻值的桥接终端电阻; 第一开关，其在接通时将桥接端接电阻器连接到传输线;以及当断开时将桥接终端电阻器与传输线路断开; 连接在传输线路和固定电压节点之间的上拉/下拉电阻器，具有分别匹配传输线路的特征阻抗，固定电压节点为电源或接地的电阻值; 以及第二开关，其在接通时将传输线和固定电压节点之间的上拉/下拉电阻连接起来，以及在断开时从传输线断开上拉/下拉电阻。
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2.发明申请公开(公告)号：US20110280322A1
公开(公告)日：2011-11-17
申请号：US13142655
申请日：2010-10-13
申请人： Hiroshi Suenaga , Osamu Shibata , Yoshiyuki Saito , Kohei Masuda , Yoshihide Komatsu , Masashi Suzuki
发明人： Hiroshi Suenaga , Osamu Shibata , Yoshiyuki Saito , Kohei Masuda , Yoshihide Komatsu , Masashi Suzuki
IPC分类号： H04B3/00
CPC分类号： H04L25/0278
摘要： A data transmission system comprises: a pair of transmission lines connecting a plurality of apparatuses; a bridge termination resistor connected between the transmission lines and having a resistance value matching a differential impedance of the transmission lines; a first switch connecting the bridge termination resistor to the transmission lines when being turned on, and disconnecting the bridge termination resistor from the transmission lines when being turned off; pull-up/down resistors connected between the transmission lines and a fixed voltage node, and having resistance values respectively matching characteristic impedances of the transmission lines, the fixed voltage node being a power supply or a ground; and second switches connecting the pull-up/down resistors between the transmission lines and the fixed voltage node when being turned on, and disconnecting the pull-up/down resistors from the transmission lines when being turned off.
摘要翻译： 数据传输系统包括：一对连接多个设备的传输线; 连接在传输线之间并具有与传输线的差分阻抗匹配的电阻值的桥接终端电阻; 第一开关，其在接通时将桥接端接电阻器连接到传输线;以及当断开时将桥接终端电阻器与传输线路断开; 连接在传输线路和固定电压节点之间的上拉/下拉电阻器，具有分别匹配传输线路的特征阻抗，固定电压节点为电源或接地的电阻值; 以及第二开关，其在接通时将传输线和固定电压节点之间的上拉/下拉电阻连接起来，以及在断开时从传输线断开上拉/下拉电阻。
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公开(公告)号：US20120021640A1
公开(公告)日：2012-01-26
申请号：US13257560
申请日：2010-04-26
申请人： Kohei Masuda , Hiroshi Suenaga , Osamu Shibata , Yoshiyuki Saito
发明人： Kohei Masuda , Hiroshi Suenaga , Osamu Shibata , Yoshiyuki Saito
IPC分类号： H01R11/00
CPC分类号： H04L25/0272
摘要： A serial-parallel conversion circuit provided on one end of a cable body converts a first serial signal into parallel signals and outputs the parallel signals to parallel signal lines. A parallel-serial conversion circuit provided on another end of the cable body converts the parallel signals inputted from the parallel signal lines into a second serial signal and outputs the second serial signal to outside.
摘要翻译： 设置在电缆体的一端的串行并行转换电路将第一串行信号转换为并行信号，并将并行信号输出到并行信号线。 在电缆体的另一端设置并行转换电路，将从并行信号线输入的并行信号变换为第二串行信号，并将第二串行信号输出到外部。
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4.发明申请DIFFERENTIAL SIGNAL TRANSMISSION LINE, IC PACKAGE, AND METHOD FOR TESTING SAID DIFFERENTIAL SIGNAL TRANSMISSION LINE AND IC PACKAGE 审中-公开差分信号传输线，IC封装和测试差分信号传输线和IC封装的方法公开(公告)号：US20120112784A1
公开(公告)日：2012-05-10
申请号：US13383726
申请日：2011-04-13
申请人： Kohei Masuda , Osamu Shibata , Hiroshi Suenaga , Yoshiyuki Saito
发明人： Kohei Masuda , Osamu Shibata , Hiroshi Suenaga , Yoshiyuki Saito
CPC分类号： H04B3/30 , G01R31/002 , H01L22/32 , H01L23/66 , H01L24/48 , H01L24/49 , H01L2223/6611 , H01L2223/6638 , H01L2224/48227 , H01L2224/48247 , H01L2224/49171 , H01L2924/00014 , H01L2924/14 , H01L2924/30107 , H01L2924/3011 , H01L2924/30111 , H04B3/46 , H04B3/50 , H04L25/0272 , H04L25/0276 , H04L25/0278 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An IC package includes an integrated circuit for transmitting and receiving a pair of differential signals composed of a signal having positive polarity and a signal having negative polarity, a first signal terminal for transmitting the signal having positive polarity, a second signal terminal for transmitting the signal having negative polarity, and a third terminal arranged between the first signal terminal and the second signal terminal. The first and second terminals are electrically connected to the integrated circuit, and the third terminal is not electrically connected to the integrated circuit.
摘要翻译： IC封装包括用于发送和接收由具有正极性的信号和具有负极性的信号组成的一对差分信号的集成电路，用于发送具有正极性的信号的第一信号端子，用于发送信号的第二信号端子 具有负极性，第三端子布置在第一信号端子和第二信号端子之间。 第一和第二端子电连接到集成电路，并且第三端子不与集成电路电连接。
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5.发明申请DRIVER CIRCUIT, RECEIVER CIRCUIT, AND METHOD OF CONTROLLING A COMMUNICATIONS SYSTEM INCLUDING THE CIRCUITS 有权驱动电路，接收电路和控制包括电路的通信系统的方法公开(公告)号：US20110268198A1
公开(公告)日：2011-11-03
申请号：US13143233
申请日：2010-11-01
IPC分类号： H04L25/00
CPC分类号： H04B1/1615 , H04L25/0272
摘要： In a communications system for differential signals, a driver circuit is connected to a receiver circuit by a pair of differential signal lines. When data is not being transmitted, the differential signal lines are maintained at a predetermined electric potential, and when data is to be transferred, a differential signal is output at predetermined electric potentials. The receiver circuit switches between a power-down state and a normal state when detecting states of the electric potentials of the differential signal lines.
摘要翻译： 在用于差分信号的通信系统中，驱动电路通过一对差分信号线连接到接收器电路。 当不发送数据时，差分信号线保持在预定电位，并且当数据要被传送时，以预定电位输出差分信号。 当检测到差分信号线的电位的状态时，接收器电路在掉电状态和正常状态之间切换。
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公开(公告)号：US20110241432A1
公开(公告)日：2011-10-06
申请号：US13139397
申请日：2010-11-01
IPC分类号： H02J4/00
CPC分类号： G06F13/42 , H04L25/0272 , Y10T307/696
摘要： To aim to provide an interface circuit that supports both a single-ended method and a differential method as a transmission method, and one of pairs of input terminals for a differential signal is shared to input/output a single-ended signal.A differential signal receiving circuit that receives a differential signal input through the pair of shared terminals is activated when a differential signal is input to a pair of dedicated input terminals for a differential signal, which is different from the pair of shared terminals. After the differential signal receiving circuit is activated, the active state is maintained by a built-in controller.Accordingly, the activation of the differential signal receiving circuit that receives a differential signal input through the shared terminals is controlled by controlling the differential signal input through the pair of dedicated input terminals, and furthermore, the possibility that the differential signal receiving circuit becomes inactive at an unexpected timing is reduced to a low level.
摘要翻译： 为了提供支持单端方法和差分方法两者的接口电路作为传输方法，并且用于差分信号的一对输入端子被共享以输入/输出单端信号。 当将差分信号输入到与一对共享终端不同的差分信号的一对专用输入端子时，接收通过一对共享端子输入的差分信号的差分信号接收电路被激活。 在差分信号接收电路被激活之后，由内置控制器维持有效状态。 因此，通过控制通过一对专用输入端子输入的差分信号来控制接收通过共享端子输入的差分信号的差分信号接收电路的激活，此外，差分信号接收电路在 意想不到的时间降到了低水平。
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公开(公告)号：US08713231B2
公开(公告)日：2014-04-29
申请号：US13139397
申请日：2010-11-01
IPC分类号： G06F13/42
CPC分类号： G06F13/42 , H04L25/0272 , Y10T307/696
摘要： To aim to provide an interface circuit that supports both a single-ended method and a differential method as a transmission method, and one of pairs of input terminals for a differential signal is shared to input/output a single-ended signal.A differential signal receiving circuit that receives a differential signal input through the pair of shared terminals is activated when a differential signal is input to a pair of dedicated input terminals for a differential signal, which is different from the pair of shared terminals. After the differential signal receiving circuit is activated, the active state is maintained by a built-in controller.Accordingly, the activation of the differential signal receiving circuit that receives a differential signal input through the shared terminals is controlled by controlling the differential signal input through the pair of dedicated input terminals, and furthermore, the possibility that the differential signal receiving circuit becomes inactive at an unexpected timing is reduced to a low level.
摘要翻译： 为了提供支持单端方法和差分方法两者的接口电路作为传输方法，并且用于差分信号的一对输入端子被共享以输入/输出单端信号。 当将差分信号输入到与一对共享终端不同的差分信号的一对专用输入端子时，接收通过一对共享端子输入的差分信号的差分信号接收电路被激活。 在差分信号接收电路被激活之后，由内置控制器维持有效状态。 因此，通过控制通过一对专用输入端子输入的差分信号来控制接收通过共享端子输入的差分信号的差分信号接收电路的激活，此外，差分信号接收电路在 意想不到的时间降到了低水平。
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8.发明授权Driver circuit, receiver circuit, and method of controlling a communications system including the circuits 有权驱动器电路，接收器电路和控制包括电路的通信系统的方法公开(公告)号：US08548070B2
公开(公告)日：2013-10-01
申请号：US13143233
申请日：2010-11-01
IPC分类号： H04B3/00
CPC分类号： H04B1/1615 , H04L25/0272
摘要： In a communications system for differential signals, a driver circuit is connected to a receiver circuit by a pair of differential signal lines. When data is not being transmitted, the differential signal lines are maintained at a predetermined electric potential, and when data is to be transferred, a differential signal is output at predetermined electric potentials. The receiver circuit switches between a power-down state and a normal state when detecting states of the electric potentials of the differential signal lines.
摘要翻译： 在用于差分信号的通信系统中，驱动电路通过一对差分信号线连接到接收器电路。 当不发送数据时，差分信号线保持在预定电位，并且当数据要被传送时，以预定电位输出差分信号。 当检测到差分信号线的电位的状态时，接收器电路在掉电状态和正常状态之间切换。
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9.发明授权Removable memory device, phase synchronizing method, phase synchronizing program, medium recording the same, and host terminal 有权可移动存储设备，相位同步方法，相位同步程序，介质记录和主机终端公开(公告)号：US07886085B2
公开(公告)日：2011-02-08
申请号：US12295051
申请日：2007-02-20
申请人： Hiroshi Suenaga , Osamu Shibata , Noriaki Takeda , Toru Iwata , Takaharu Yoshida , Yoshiyuki Saito
发明人： Hiroshi Suenaga , Osamu Shibata , Noriaki Takeda , Toru Iwata , Takaharu Yoshida , Yoshiyuki Saito
摘要： An object of the present invention is to provide a technique to improve the data transmission efficiency which allows correct reception of the data at the same time. A removable memory device that transmits/receives data to and from a host terminal, which includes: a clock reception section that receives a transmission/reception clock, which is used for transmitting/receiving data between the host terminal and the removable memory device, from the host terminal; a phase synchronization pattern generation section that generates a phase synchronization pattern, which is for adjusting a phase of internal reception clock which the host terminal incorporates for receiving data from the removable memory device, based on the transmission/reception clock; and a transmission section that transmits the generated phase synchronization pattern to the host terminal, and in which the phase synchronization pattern includes a first level signal which lasts for at least two cycles, and a second level signal which follows the first level signal and lasts for one cycle, is provided.
摘要翻译： 本发明的目的是提供一种提高数据传输效率的技术，其允许同时正确地接收数据。 一种向主机终端发送/接收数据的可移动存储装置，包括：接收用于在主机终端和可移动存储装置之间发送/接收数据的发送/接收时钟的时钟接收部分， 主机终端; 相位同步模式生成部，其基于所述发送接收时钟生成相位同步模式，所述相位同步模式用于调整所述主机终端结合的用于从所述可移动存储装置接收数据的内部接收时钟的相位; 以及发送部，其将所生成的相位同步模式发送到所述主机终端，并且所述相位同步模式包括持续至少两个周期的第一电平信号，以及在所述第一电平信号之后持续的第二电平信号， 提供一个循环。
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公开(公告)号：US07899960B2
公开(公告)日：2011-03-01
申请号：US12402016
申请日：2009-03-11
申请人： Osamu Shibata , Hiroshi Suenaga , Yoshiyuki Saito
发明人： Osamu Shibata , Hiroshi Suenaga , Yoshiyuki Saito
CPC分类号： G06F13/1689
摘要： A card controller receives data from a recording card via a socket. A read clock is transmitted in a main transmission wiring, and the data is transmitted in a data transmission wiring. The read clock is withdrawn from the card controller by an outgoing transmission wiring and retrieved into the card controller by an incoming transmission wiring. A transmission delay amount of the outgoing transmission wiring is equal to that of the main transmission wiring, and a transmission delay amount of the incoming transmission wiring is equal to that of the data transmission wiring. The card controller receives the data in synchronization with the read clock retrieved by the incoming transmission wiring.
摘要翻译： 卡控制器通过插座从记录卡接收数据。 在主发送配线中发送读时钟，在数据发送配线中发送数据。 读出时钟通过输出的传输线从卡控制器中取出，并通过输入的传输线被取回到卡控制器中。 输出发送线路的发送延迟量与主发送配线的发送延迟量相同，输入发送配线的发送延迟量与数据发送配线的发送延迟量相同。 卡控制器与由输入的传输线路检索的读取时钟同步地接收数据。
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