公开(公告)号：US4616148A

公开(公告)日：1986-10-07

申请号：US792854

申请日：1985-10-30

申请人： Kiyofumi Ochii ,  Hiroshi Yasuda ,  Fujio Masuoka

发明人： Kiyofumi Ochii ,  Hiroshi Yasuda ,  Fujio Masuoka

IPC分类号： H03F3/345 ,  G11C7/06 ,  G11C11/419 ,  H03F3/34 ,  H03K3/356 ,  H03K5/24 ,  H03K3/023

CPC分类号： G11C7/065 ,  G11C7/062 ,  H03K3/356104

摘要： A sense amplifier in use for a memory device is made up of a pair of Schmitt trigger circuits. These Schmitt trigger circuits are cross coupled with each other so that each of the Schmitt trigger circuits operates in response to a predetermined high potential difference. The predetermined potential difference is high enough to operate each Schmitt trigger circuit according to the steeper slope of the two long slopes of a hysteresis loop of the Schmitt trigger circuit.

摘要翻译： 用于存储器件的读出放大器由一对施密特触发电路组成。 这些施密特触发电路彼此交叉耦合，使得施密特触发电路中的每一个响应于预定的高电位差工作。 预定的电位差足够高以根据施密特触发电路的磁滞回线的两个较大斜率的较陡斜率来操作每个施密特触发电路。

公开(公告)号：US4687954A

公开(公告)日：1987-08-18

申请号：US708508

申请日：1985-03-05

申请人： Hiroshi Yasuda ,  Kiyofumi Ochii ,  Fujio Masuoka

发明人： Hiroshi Yasuda ,  Kiyofumi Ochii ,  Fujio Masuoka

IPC分类号： H03K3/3565 ,  H03K3/356

CPC分类号： H03K3/3565

摘要： A transistor circuit with hysteresis operation, which is formed with a detector part and selector part. The detector part detects a change in the level of an input signal according to one of first and second threshold levels, and generates an output signal having a level corresponding to the input signal. The level of the input signal is changed between a first level and a second level which is lower than the first level. The first and second threshold levels fall within a range defined between the first and second levels. The selector part selects one of the first and second threshold levels in accordance with the level of the output signal, and applies the selected one threshold level to the detector part.

摘要翻译： 具有迟滞操作的晶体管电路，其形成有检测器部​​分和选择器部分。 检测器部分根据第一和第二阈值电平之一检测输入信号电平的变化，并产生具有与输入信号对应的电平的输出信号。 输入信号的电平在低于第一电平的第一电平和第二电平之间改变。 第一和第二阈值水平落在第一和第二水平之间限定的范围内。 选择器部分根据输出信号的电平来选择第一和第二阈值电平中的一个，并将所选择的一个阈值电平施加到检测器部分。

公开(公告)号：US4710897A

公开(公告)日：1987-12-01

申请号：US726698

申请日：1985-04-24

申请人： Fujio Masuoka ,  Kiyofumi Ochii

发明人： Fujio Masuoka ,  Kiyofumi Ochii

IPC分类号： H01L29/94 ,  H01L23/532 ,  H01L27/11 ,  H01L27/10 ,  G11C11/40 ,  H01L23/50 ,  H01L29/04

CPC分类号： H01L27/1104 ,  H01L23/53271 ,  H01L2924/0002 ,  Y10S257/903

摘要： The gate electrode of a first CMOS inverter is connected to the drains of each transistor of a second CMOS inverter via an interconnection, and the gate electrode of the second CMOS inverter is connected to the drains of the first CMOS inverter via an interconnection, to form a flip-flop circuit. A pair of transfer transistors are connected to the nodes of this flip-flop circuit. A plurality of memory cells each constructed by the flip-flop circuit and the pair of transfer transistors are integrated in a matrix form to form a semiconductor memory device. The pair of gate electrodes are formed of a first polycrystalline silicon layer which includes an impurity of the first conductivity type. The pair of interconnections are formed of an impurity-doped second polycrystalline silicon layer and a high-melting point metal layer, and formed on a first interlayer insulation film. The high-melting point metal layer is provided to prevent an increase in the resistance value due to the formation of a pn junction formed by the interconnections.

摘要翻译： 第一CMOS反相器的栅电极通过互连连接到第二CMOS反相器的每个晶体管的漏极，并且第二CMOS反相器的栅电极经由互连连接到第一CMOS反相器的漏极，以形成 触发电路。 一对传输晶体管连接到该触发器电路的节点。 由触发器电路和一对转移晶体管构成的多个存储单元以矩阵形式集成以形成半导体存储器件。 一对栅电极由包括第一导电类型的杂质的第一多晶硅层形成。 一对互连由杂质掺杂的第二多晶硅层和高熔点金属层形成，并形成在第一层间绝缘膜上。 提供高熔点金属层以防止由互连形成的pn结的形成导致的电阻值的增加。

公开(公告)号：US4814841A

公开(公告)日：1989-03-21

申请号：US9559

申请日：1987-01-30

申请人： Fujio Masuoka ,  Kiyofumi Ochii

发明人： Fujio Masuoka ,  Kiyofumi Ochii

IPC分类号： H01L21/8238 ,  H01L27/06 ,  H01L27/092 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L27/0688 ,  H01L27/0922 ,  Y10S257/903

摘要： A semiconductor device which comprises an N channel MOS transistor deposited on a P conductivity substrate, a P channel MOS transistor mounted on said N channel MOS transistor, and a high melting metal layer interposed between the drain regions of said first and second MOS transistors in a direction perpendicular to the surface of said semiconductor device to thereby effect ohmic contact between said drain regions.

摘要翻译： 一种半导体器件，其包括沉积在P导电性基板上的N沟道MOS晶体管，安装在所述N沟道MOS晶体管上的P沟道MOS晶体管，以及插入在所述第一和第二MOS晶体管的漏极区域之间的高熔点金属层， 方向垂直于所述半导体器件的表面，从而实现所述漏极区之间的欧姆接触。

公开(公告)号：US4779014A

公开(公告)日：1988-10-18

申请号：US095263

申请日：1987-09-11

申请人： Fujio Masuoka ,  Kiyofumi Ochii

发明人： Fujio Masuoka ,  Kiyofumi Ochii

IPC分类号： H03K19/08 ,  H03K19/00 ,  H03K19/013 ,  H03K19/0944 ,  H03K17/04

CPC分类号： H03K19/0136 ,  H03K19/001 ,  H03K19/09448

摘要： A logic circuit comprises at least one signal input terminal, an output terminal, an output circuit including a first bipolar transistor coupled between the output terminal and a reference potential terminal, to discharge the output terminal, and an MOS type logic circuit for supplying to the base of the first bipolar transistor a signal of a level corresponding to an input signal supplied to the at least one signal input terminal. The logic circuit further comprises a control MOS transistor coupled between a power source terminal and the base of the bipolar transistor, for supplying part of the base current to the bipolar transistor in response to a signal at the output terminal.

公开(公告)号：US4903096A

公开(公告)日：1990-02-20

申请号：US265276

申请日：1988-10-25

申请人： Fujio Masuoka ,  Kiyofumi Ochii

发明人： Fujio Masuoka ,  Kiyofumi Ochii

IPC分类号： H01L23/532 ,  H01L27/11

CPC分类号： H01L23/53271 ,  H01L27/1112 ,  H01L2924/0002 ,  Y10S257/915

摘要： There is disclosed a memory cell in which a low resistance polycrystal silicon layer and a high resistance polycrystal silicon layer are connected to each other with a barrier metal layer provided therebetween and formed in a contact hole of an insulation film.

摘要翻译： 公开了一种存储单元，其中低电阻多晶硅层和高电阻多晶硅层彼此连接，其间设置有阻挡金属层，并形成在绝缘膜的接触孔中。

公开(公告)号：US08901640B2

公开(公告)日：2014-12-02

申请号：US12944310

申请日：2010-11-11

申请人： Fujio Masuoka ,  Tomohiko Kudo

发明人： Fujio Masuoka ,  Tomohiko Kudo

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC分类号： H01L29/7827 ,  H01L21/823431 ,  H01L29/0657 ,  H01L29/42356 ,  H01L29/42364 ,  H01L29/42372 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/78642

摘要： The object of the invention is to provide a semiconductor device realizing high-speed operation of surrounding gate transistors (SGTs), which are three-dimensional semiconductors, by increasing the ON current of the SGTs. This object is achieved by a semiconductor element being provided in which a source, a drain and a gate are positioned in layers on a substrate, the semiconductor element being provided with: a silicon column; an insulating body surrounding the side surface of the silicon column; a gate surrounding the insulating body; a source region positioned above or below the silicon column; and a drain region positioned below or above the silicon column; wherein the contact surface of the silicon column with the source region is smaller than the contact surface of the silicon column with the drain region.

摘要翻译： 本发明的目的是通过增加SGT的导通电流来提供实现作为三维半导体的周围栅极晶体管（SGT）的高速操作的半导体器件。 该目的通过提供一种半导体元件来实现，其中源极，漏极和栅极分层地定位在衬底上，半导体元件设置有硅柱; 围绕所述硅柱的侧表面的绝缘体; 围绕绝缘体的门; 位于硅柱上方或下方的源区; 以及位于硅柱下方或上方的漏极区域; 其中所述硅柱与所述源极区域的接触表面小于所述硅柱与所述漏极区的接触表面。

公开(公告)号：US08772881B2

公开(公告)日：2014-07-08

申请号：US12794088

申请日：2010-06-04

申请人： Fujio Masuoka ,  Hiroki Nakamura

发明人： Fujio Masuoka ,  Hiroki Nakamura

IPC分类号： H01L27/11 ,  H01L27/088

CPC分类号： H01L27/1104 ,  H01L27/0207 ,  H01L27/11

摘要： The object to provide a highly-integrated SGT-based SRAM is achieved by forming an SRAM using an inverter which comprises a first island-shaped semiconductor layer, a first gate dielectric film in contact with a periphery of the first island-shaped semiconductor layer, a first gate electrode having one surface in contact with the first gate dielectric film, a second gate dielectric film in contact with another surface of the first gate electrode, a first arc-shaped semiconductor layer in contact with the second gate dielectric film, a first first-conductive-type high-concentration semiconductor layer arranged on a top of the first island-shaped semiconductor layer, a second first-conductive-type high-concentration semiconductor layer arranged underneath the first island-shaped semiconductor layer, a first second-conductive-type high-concentration semiconductor layer arranged on a top of the first arc-shaped semiconductor layer, and a second second-conductive-type high-concentration semiconductor layer arranged underneath the first arc-shaped semiconductor layer.

摘要翻译： 提供高度集成的基于SGT的SRAM的目的是通过使用逆变器形成SRAM来实现，该逆变器包括第一岛状半导体层，与第一岛状半导体层的周边接触的第一栅极电介质膜， 具有与第一栅极电介质膜接触的一个表面的第一栅极电极，与第一栅电极的另一表面接触的第二栅极电介质膜，与第二栅极电介质膜接触的第一弧形半导体层，第一栅极电极 布置在第一岛状半导体层的顶部上的第一导电型高浓度半导体层，布置在第一岛状半导体层下方的第二第一导电型高浓度半导体层，第一导电型高浓度半导体层，第一导电型高浓度半导体层， 布置在第一弧形半导体层的顶部上的高浓度半导体层和第二第二导电型高浓度半导体层 所述半导体层布置在所述第一弧形半导体层下方。

公开(公告)号：US08564034B2

公开(公告)日：2013-10-22

申请号：US13606823

申请日：2012-09-07

申请人： Fujio Masuoka ,  Nozomu Harada

发明人： Fujio Masuoka ,  Nozomu Harada

IPC分类号： H01L31/062

CPC分类号： H01L27/14616 ,  H01L27/14614

摘要： In a solid-state imaging device, a pixel has a first island-shaped semiconductor (P11) formed on a substrate (1) and a drive output circuit has second island-shaped semiconductors (4a to 4c) formed on the substrate at the same height as that of the first island-shaped semiconductor (P11). The first island-shaped semiconductor (P11) has a first gate insulating layer (6b) formed on an outer periphery thereof and a first gate conductor layer (105a) surrounding the first gate insulating layer (6b). The second island-shaped semiconductors (4a to 4c) have a second gate insulating layer (6a) formed on an outer periphery thereof and a second gate conductor layer (7a) surrounding the second gate insulating layer (6a). The first gate conductor layer (105a) and the second gate conductor layer (7a) have bottom portions located on the same plane.

摘要翻译： 在固态成像装置中，像素具有形成在基板（1）上的第一岛状半导体（P11），驱动输出电路具有形成在基板上的第二岛状半导体（4a〜4c） 高度为第一岛状半导体（P11）的高度。 第一岛状半导体（P11）具有形成在其外周上的第一栅极绝缘层（6b）和围绕第一栅极绝缘层（6b）的第一栅极导体层（105a）。 第二岛状半导体（4a〜4c）具有在其外周形成的第二栅极绝缘层（6a）和围绕第二栅极绝缘层（6a）的第二栅极导体层（7a）。 第一栅极导体层（105a）和第二栅极导体层（7a）具有位于同一平面上的底部。

公开(公告)号：US08558317B2

公开(公告)日：2013-10-15

申请号：US12854564

申请日：2010-08-11

申请人： Fujio Masuoka ,  Hiroki Nakamura

发明人： Fujio Masuoka ,  Hiroki Nakamura

IPC分类号： H01L27/092

CPC分类号： H01L21/823885 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/823857 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12

摘要： The object to provide a semiconductor device comprising a highly-integrated SGT-based CMOS inverter circuit is achieved by forming an inverter which comprises: a first transistor including; an first island-shaped semiconductor layer; a first gate insulating film; a gate electrode; a first first-conductive-type high-concentration semiconductor layer arranged above the first island-shaped semiconductor layer; and a second first-conductive-type high-concentration semiconductor layer arranged below the first island-shaped semiconductor layer, and a second transistor including; a second gate insulating film surrounding a part of the periphery of the gate electrode; a second semiconductor layer in contact with a part of the periphery of the second gate insulating film; a first second-conductive-type high-concentration semiconductor layer arranged above the second semiconductor layer; and a second second-conductive-type high-concentration semiconductor layer arranged below the second semiconductor layer.