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    Semiconductor device
    2.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US09111934B2

    公开(公告)日：2015-08-18

    申请号：US13137032

    申请日：2011-07-15

    申请人： Hiroshi Tsuda ,  Yoshitaka Kubota ,  Hiromichi Takaoka

    发明人： Hiroshi Tsuda ,  Yoshitaka Kubota ,  Hiromichi Takaoka

    IPC分类号： H01L23/52 ,  H01L23/525

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device includes an electric fuse and first and second large area wirings for applying a voltage to the electric fuse. The electric fuse includes a fuse unit which includes an upper-layer fuse wiring, a lower-layer fuse wiring, and a via connecting the upper-layer fuse wiring and the lower-layer fuse wiring, an upper-layer lead-out wiring which connects the upper-layer fuse wiring and the first large area wiring and has a bent pattern, and a lower-layer lead-out wiring which connects the lower-layer fuse wiring and the second large area wiring and has a bent pattern.

    摘要翻译： 半导体器件包括电熔丝和用于向电熔丝施加电压的第一和第二大面积布线。 电熔丝包括熔丝单元，其包括上层熔丝布线，下层熔丝布线和连接上层熔丝布线和下层熔丝布线的布线，上层引出布线 连接上层熔丝布线和第一大面积布线并具有弯曲图案，以及连接下层熔丝布线和第二大面积布线并具有弯曲图案的下层引出布线。

    Semiconductor device
    5.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08080861B2

    公开(公告)日：2011-12-20

    申请号：US12588202

    申请日：2009-10-07

    申请人： Hiroshi Tsuda ,  Yoshitaka Kubota ,  Hiromichi Takaoka

    发明人： Hiroshi Tsuda ,  Yoshitaka Kubota ,  Hiromichi Takaoka

    IPC分类号： H01L23/52

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device includes an electric fuse and first and second large area wirings for applying a voltage to the electric fuse. The electric fuse includes a fuse unit which includes an upper-layer fuse wiring, a lower-layer fuse wiring, and a via connecting the upper-layer fuse wiring and the lower-layer fuse wiring, an upper-layer lead-out wiring which connects the upper-layer fuse wiring and the first large area wiring and has a bent pattern, and a lower-layer lead-out wiring which connects the lower-layer fuse wiring and the second large area wiring and has a bent pattern.

    摘要翻译： 半导体器件包括电熔丝和用于向电熔丝施加电压的第一和第二大面积布线。 电熔丝包括熔丝单元，其包括上层熔丝布线，下层熔丝布线和连接上层熔丝布线和下层熔丝布线的布线，上层引出布线 连接上层熔丝布线和第一大面积布线并具有弯曲图案，以及连接下层熔丝布线和第二大面积布线并具有弯曲图案的下层引出布线。

    Semiconductor device including first and second sidewalls and method of manufacturing semiconductor device
    7.
    发明授权
    Semiconductor device including first and second sidewalls and method of manufacturing semiconductor device 有权
    包括第一和第二侧壁的半导体器件和制造半导体器件的方法

    公开(公告)号：US07842576B2

    公开(公告)日：2010-11-30

    申请号：US12588931

    申请日：2009-11-03

    申请人： Yoshitaka Kubota

    发明人： Yoshitaka Kubota

    IPC分类号： H01L21/336

    CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L27/11573 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/66833

    摘要： The invention provides a method of manufacturing a semiconductor device including a non-volatile memory with high yield, and a semiconductor device manufactured by the method. A method of manufacturing a semiconductor device includes a process of forming a second side wall such that the width of the second side wall, which is formed on the side of a portion of a second gate electrode that does not face dummy gates on a drain forming region side, in a gate length direction is larger than that of the second side wall, which is formed on the side of the second gate electrode on a source forming region side, in the gate length direction, in a non-volatile memory forming region.

    摘要翻译： 本发明提供了一种制造包括具有高产率的非易失性存储器的半导体器件的方法以及通过该方法制造的半导体器件。 一种制造半导体器件的方法包括形成第二侧壁的工艺，使得形成在第二栅电极的不在漏极形成上的虚拟栅极的一侧的一侧上的第二侧壁的宽度 在栅极长度方向上的栅极长度方向的栅极长度方向上的栅极长度方向上的栅极长度方向上的栅极长度方向上的栅极长度方向上的栅极长度方向上的栅极长度方向上， 。

    Electrical fuse, semiconductor device and method of disconnecting electrical fuse
    8.
    发明申请
    Electrical fuse, semiconductor device and method of disconnecting electrical fuse 失效
    电气保险丝，半导体装置及断开电气保险丝的方法

    公开(公告)号：US20090231020A1

    公开(公告)日：2009-09-17

    申请号：US12453053

    申请日：2009-04-28

    申请人： Yoshitaka Kubota

    发明人： Yoshitaka Kubota

    IPC分类号： H01H85/00 ,  H01L23/525

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An electrical fuse including a polysilicon layer; a silicide layer formed over the polysilicon layer; and a first metal contact and a second metal contact arranged over the silicide layer, while being spaced from each other, the electrical fuse being configured so that the silicide layer, after disconnection, is excluded from a region right under the second metal contact, and from a region between the second metal contact and the first metal contact is provided.

    摘要翻译： 包括多晶硅层的电熔丝; 形成在所述多晶硅层上的硅化物层; 以及设置在所述硅化物层上方的第一金属触点和第二金属触点，并且彼此间隔开，所述电熔丝被构造成使得所述硅化物层在断开之后被排除在所述第二金属触点正下方的区域中，以及 提供从第二金属触点和第一金属触点之间的区域。

    Vapor deposition material
    9.
    发明授权
    Vapor deposition material 失效
    气相沉积材料

    公开(公告)号：US5789330A

    公开(公告)日：1998-08-04

    申请号：US874341

    申请日：1997-06-13

    申请人： Satoshi Kondo ,  Yoshitaka Kubota

    发明人： Satoshi Kondo ,  Yoshitaka Kubota

    IPC分类号： C04B35/486 ,  C23C14/08 ,  C23C14/24 ,  C04B35/48

    CPC分类号： C04B35/486 ,  C23C14/083 ,  C23C14/24 ,  Y02T50/67

    摘要： A vapor deposition material which is a sintered body of zirconia containing a stabilizer, wherein the content of monoclinic phase is from 25 to 70%, the content of tetragonal phase is at most 3% and the rest is cubic phase, and of which the bulk density is from 3.0 to 5.0 g/cm.sup.3, the porosity is from 15 to 50%, the mode size of pores is from 0.5 to 3 .mu.m, and the volume of pores of from 0.1 to 5 .mu.m constitutes at least 90% of the total pore volume.

    摘要翻译： 作为含有稳定剂的氧化锆烧结体的气相沉积材料，其中单斜相含量为25〜70％，四方相为3％以下，其余为立方相，其中体积 密度为3.0〜5.0g / cm 3，孔隙率为15〜50％，孔的模尺寸为0.5〜3μm，孔的体积为0.1〜5μm构成至少90％ 总孔体积。