公开(公告)号：US20140284734A1

公开(公告)日：2014-09-25

申请号：US13965149

申请日：2013-08-12

申请人： Hiroyuki KANAYA ,  Kuniaki SUGIURA

发明人： Hiroyuki KANAYA ,  Kuniaki SUGIURA

IPC分类号： H01L43/02

CPC分类号： H01L43/02 ,  H01L27/228 ,  H01L43/08

摘要： According to one embodiment, a magnetic random access memory includes a magnetoresistive element, a contact arranged under the magnetoresistive element and connected to the magnetoresistive element, and an insulating film continuously formed from a periphery of the contact to a side surface of the magnetoresistive element and including a protective portion covering the side surface of the magnetoresistive element.

摘要翻译： 根据一个实施例，磁性随机存取存储器包括磁阻元件，布置在磁阻元件下方并连接到磁阻元件的触点，以及从触点的周边连续形成到磁阻元件的侧表面的绝缘膜，以及 包括覆盖磁阻元件的侧表面的保护部分。

公开(公告)号：US20100197044A1

公开(公告)日：2010-08-05

申请号：US12699721

申请日：2010-02-03

申请人： Takeshi KAJIYAMA ,  Yoshiaki ASAO ,  Minoru AMANO ,  Shigeki TAKAHASHI ,  Masayoshi IWAYAMA ,  Kuniaki SUGIURA

发明人： Takeshi KAJIYAMA ,  Yoshiaki ASAO ,  Minoru AMANO ,  Shigeki TAKAHASHI ,  Masayoshi IWAYAMA ,  Kuniaki SUGIURA

IPC分类号： H01L21/28 ,  B28B17/00

CPC分类号： H01L43/12 ,  G11C11/161 ,  H01L27/228

摘要： A magnetic material of a magnetoresistive element is formed on a lower electrode. An upper electrode is formed on the magnetic material. A resist for nano-imprint lithography is formed on the upper electrode. A first pattern or a second pattern is formed in the resist by setting a first template or a second template into contact with the resist and curing the resist. The first template has the first pattern that corresponds to the magnetoresistive element and the lower electrode. The second template has the second pattern that corresponds to the magnetoresistive element and the upper electrode. The magnetic material and the lower electrode are patterned at the same time by using the resist having the first pattern, or the magnetic material and the upper electrode are patterned at the same time by using the resist having the second pattern.

摘要翻译： 磁阻元件的磁性材料形成在下电极上。 在磁性材料上形成上部电极。 在上电极上形成用于纳米压印光刻的抗蚀剂。 通过将第一模板或第二模板与抗蚀剂接触并固化抗蚀剂，在抗蚀剂中形成第一图案或第二图案。 第一模板具有对应于磁阻元件和下电极的第一图案。 第二模板具有对应于磁阻元件和上电极的第二图案。 通过使用具有第一图案的抗蚀剂，同时对磁性材料和下电极进行图案化，或者通过使用具有第二图案的抗蚀剂同时对磁性材料和上部电极进行图案化。

公开(公告)号：US20150069550A1

公开(公告)日：2015-03-12

申请号：US14200670

申请日：2014-03-07

申请人： Kuniaki SUGIURA ,  Tadashi KAI

发明人： Kuniaki SUGIURA ,  Tadashi KAI

IPC分类号： H01L43/02 ,  H01L43/12

CPC分类号： H01L43/12 ,  H01L43/08

摘要： According to one embodiment, a magnetoresistive element is disclosed. The element includes a lower electrode, a stacked body provided on the lower electrode and including a first magnetic layer, a tunnel barrier layer and a second magnetic layer. The first magnetic layer is under the tunnel barrier layer, the second magnetic layer is on the tunnel barrier layer. The first magnetic layer includes a first region and a second region outside the first region to surround the first region. The second region includes an element in the first region and other element being different from the element.

摘要翻译： 根据一个实施例，公开了一种磁阻元件。 元件包括下电极，设置在下电极上并包括第一磁性层，隧道势垒层和第二磁性层的层叠体。 第一磁性层位于隧道势垒层下方，第二磁性层位于隧道势垒层上。 第一磁性层包括第一区域和第一区域之外的第二区域以围绕第一区域。 所述第二区域包括所述第一区域中的元件，并且所述元件与所述元件不同。

公开(公告)号：US20110215382A1

公开(公告)日：2011-09-08

申请号：US13035168

申请日：2011-02-25

申请人： Yoshiaki ASAO ,  Takeshi KAJIYAMA ,  Kuniaki SUGIURA

发明人： Yoshiaki ASAO ,  Takeshi KAJIYAMA ,  Kuniaki SUGIURA

IPC分类号： H01L29/82

CPC分类号： H01L29/82

摘要： According to one embodiment, a semiconductor memory device is disclosed. The device includes MOSFET1 and MOSFET2 arranged in a first direction, variable resistive element (hereafter R1) above MOSFET1 and MOSFET2, a lower end of the R1 being connected to drains of MOSFET1 and MOSFET2, MOSFET3 and MOSFET4 arranged in the first direction, variable resistive element (hereafter R2) above MOSFET3 and MOSFET4, and a lower end of the R2 being connected to drains of MOSFET3 and MOSFET4. The device further includes first wiring line extending in the first direction and connected to sources of MOSFET1 and MOSFET2, second wiring line extending in the first direction and connected to sources of MOSFET3 and MOSFET4, upper electrode connecting upper end of the R1 and upper end of the R2, and third wiring line extending in the first direction and connected to the upper electrode.

摘要翻译： 根据一个实施例，公开了一种半导体存储器件。 该器件包括在第一方向上布置的MOSFET1和MOSFET2，MOSFET1和MOSFET2上方的可变电阻元件（以下称为R1），R1的下端连接到沿第一方向布置的MOSFET1和MOSFET2，MOSFET3和MOSFET4的漏极，可变电阻 元件（以下称为R2），MOSFET3和MOSFET4之上，R2的下端连接到MOSFET3和MOSFET4的漏极。 该器件还包括沿第一方向延伸并连接到MOSFET1和MOSFET2的源极的第一布线，第二布线沿第一方向延伸并连接到MOSFET3和MOSFET4的源极，上电极连接R1的上端和上端 R2和第三布线沿第一方向延伸并连接到上电极。

公开(公告)号：US20110037108A1

公开(公告)日：2011-02-17

申请号：US12854724

申请日：2010-08-11

申请人： Kuniaki SUGIURA ,  Yoshiaki ASAO ,  Takeshi KAJIYAMA

发明人： Kuniaki SUGIURA ,  Yoshiaki ASAO ,  Takeshi KAJIYAMA

IPC分类号： H01L29/82 ,  H01L21/02

CPC分类号： H01L27/228 ,  H01L43/08 ,  H01L43/12

摘要： According to one embodiment, a magnetoresistive memory includes first and second contact plugs in a first interlayer insulating film, a lower electrode on the first interlayer insulating film, a magnetoresistive effect element on the lower electrode, and an upper electrode on the magnetoresistive effect element. The lower electrode has a tapered cross-sectional shape in which a dimension of a bottom surface of the lower electrode is longer than a dimension of an upper surface of the lower electrode, one end of the lower electrode is in contact with an upper surface of the first contact plug. The magnetoresistive effect element is provided at a position shifted from a position immediately above the first contact plug in a direction parallel to a surface of the semiconductor substrate.

摘要翻译： 根据一个实施例，磁阻存储器包括第一层间绝缘膜中的第一和第二接触插塞，第一层间绝缘膜上的下电极，下电极上的磁阻效应元件和磁阻效应元件上的上电极。 下电极具有锥形横截面形状，其中下电极的底表面的尺寸比下电极的上表面的尺寸长，下电极的一端与上电极的上表面接触 第一个接触插头。 磁阻效应元件设置在与第一接触插塞正上方的位置在平行于半导体衬底的表面的方向上偏移的位置处。

公开(公告)号：US20150069551A1

公开(公告)日：2015-03-12

申请号：US14200742

申请日：2014-03-07

申请人： Masaru TOKO ,  Masahiko NAKAYAMA ,  Kuniaki SUGIURA ,  Yutaka HASHIMOTO ,  Tadashi KAI ,  Akiyuki MURAYAMA ,  Tatsuya KISHI

发明人： Masaru TOKO ,  Masahiko NAKAYAMA ,  Kuniaki SUGIURA ,  Yutaka HASHIMOTO ,  Tadashi KAI ,  Akiyuki MURAYAMA ,  Tatsuya KISHI

IPC分类号： H01L43/02 ,  H01L43/12

CPC分类号： H01L43/12 ,  H01L27/228 ,  H01L43/08

摘要： According to one embodiment, a magnetoresistive element is disclosed. The magnetoresistive element includes a reference layer. The reference layer includes a first region, and a second region provided outside the first region to surround the same. The second region contains an element contained in the first region and another element being different from the element. The magnetoresistive element further includes a storage layer, and a tunnel barrier layer provided between the reference layer and the storage layer. The storage layer is free from the another element.

摘要翻译： 根据一个实施例，公开了一种磁阻元件。 磁阻元件包括参考层。 参考层包括第一区域和设置在第一区域外部以包围该第一区域的第二区域。 第二区域包含包含在第一区域中的元素，而另一元素与元素不同。 磁阻元件还包括存储层，以及设置在参考层和存储层之间的隧道势垒层。 存储层没有另一个元素。

公开(公告)号：US20100078763A1

公开(公告)日：2010-04-01

申请号：US12559446

申请日：2009-09-14

申请人： Keiji HOSOTANI ,  Yoshiaki ASAO ,  Kuniaki SUGIURA ,  Masatoshi YOSHIKAWA ,  Sumio IKEGAWA ,  Shigeki TAKAHASHI ,  Minoru AMANO

发明人： Keiji HOSOTANI ,  Yoshiaki ASAO ,  Kuniaki SUGIURA ,  Masatoshi YOSHIKAWA ,  Sumio IKEGAWA ,  Shigeki TAKAHASHI ,  Minoru AMANO

IPC分类号： H01L29/86 ,  H01L21/8239

CPC分类号： H01L43/08 ,  G11C11/161

摘要： A resistance-change memory includes an interlayer insulating film, a lower electrode layer, a fixed layer, a first insulating film, a recording layer, a second insulating film, a conducting layer and an interconnect. The interlayer insulating film is formed on a semiconductor substrate and has a step. The lower electrode layer is formed on the interlayer insulating film including the step. The fixed layer is formed on the lower electrode layer and has invariable magnetization. The first insulating film is formed on the fixed layer. The recording layer is formed on part of the first insulating film and has variable magnetization. The second insulating film is over the recording layer and in contact with the first insulating film. The conducting layer is formed on the second insulating film. The interconnect is connected to the conducting layer.

摘要翻译： 电阻变化存储器包括层间绝缘膜，下电极层，固定层，第一绝缘膜，记录层，第二绝缘膜，导电层和互连。 层间绝缘膜形成在半导体基板上并具有台阶。 包括该步骤的层间绝缘膜上形成下电极层。 固定层形成在下电极层上，具有不变的磁化。 第一绝缘膜形成在固定层上。 记录层形成在第一绝缘膜的一部分上并且具有可变的磁化强度。 第二绝缘膜在记录层上方并与第一绝缘膜接触。 导电层形成在第二绝缘膜上。 互连连接到导电层。

公开(公告)号：US20160104834A1

公开(公告)日：2016-04-14

申请号：US14629120

申请日：2015-02-23

申请人： Masaru TOKO ,  Kuniaki SUGIURA ,  Yutaka HASHIMOTO ,  Katsuya NISHIYAMA ,  Tadashi KAI

发明人： Masaru TOKO ,  Kuniaki SUGIURA ,  Yutaka HASHIMOTO ,  Katsuya NISHIYAMA ,  Tadashi KAI

IPC分类号： H01L43/12 ,  H01L43/02 ,  H01L43/08

CPC分类号： H01L43/12 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08

摘要： According to one embodiment, a manufacturing method of a magnetoresistive memory device includes forming a first magnetic layer on a substrate, forming a magnetoresistive effect element on the first magnetic layer, forming a mask on a part of the magnetoresistive effect element, selectively etching the magnetoresistive effect element using the mask, forming a sidewall insulating film on a sidewall of the magnetoresistive effect element exposed by the etching, selectively etching the first magnetic layer using the mask and the sidewall insulating film and forming a deposition layer containing a magnetic material on a sidewall of the first magnetic layer and the sidewall insulating film, and introducing ions into the deposition layer.

摘要翻译： 根据一个实施例，磁阻存储器件的制造方法包括在衬底上形成第一磁性层，在第一磁性层上形成磁阻效应元件，在磁阻效应元件的一部分上形成掩模，选择性地蚀刻磁阻 使用该掩模，在通过蚀刻暴露的磁阻效应元件的侧壁上形成侧壁绝缘膜，使用掩模和侧壁绝缘膜选择性地蚀刻第一磁性层，并在侧壁上形成含有磁性材料的沉积层 的第一磁性层和侧壁绝缘膜，并将离子引入沉积层。

公开(公告)号：US20110254112A1

公开(公告)日：2011-10-20

申请号：US13015410

申请日：2011-01-27

申请人： Takaya YAMANAKA ,  Yoshiaki ASAO ,  Takeshi KAJIYAMA ,  Minoru AMANO ,  Masayoshi IWAYAMA ,  Kuniaki SUGIURA ,  Yukinori KOYAMA

发明人： Takaya YAMANAKA ,  Yoshiaki ASAO ,  Takeshi KAJIYAMA ,  Minoru AMANO ,  Masayoshi IWAYAMA ,  Kuniaki SUGIURA ,  Yukinori KOYAMA

IPC分类号： H01L29/82 ,  H01L21/4763

CPC分类号： H01L27/228 ,  H01L21/7684 ,  H01L43/12

摘要： A semiconductor memory device includes a semiconductor substrate, and plural switching transistors provided on the semiconductor substrate. A contact plug is embedded between the adjacent two switching transistors described above, is insulated from gates of the adjacent two switching transistors, and is electrically connected to diffusion layers of the adjacent two switching transistors. An upper connector is formed on the contact plug, and an upper surface is at a position higher than upper surfaces of the switching transistors. A memory element is provided on the upper surface of the upper connector, and stores data. A wiring is provided on the memory element.

摘要翻译： 半导体存储器件包括半导体衬底和设置在半导体衬底上的多个开关晶体管。 接触插头嵌入在上述相邻的两个开关晶体管之间，与相邻的两个开关晶体管的栅极绝缘，并且电连接到相邻的两个开关晶体管的扩散层。 在接触插塞上形成上连接器，上表面位于高于开关晶体管的上表面的位置。 存储元件设置在上连接器的上表面上并存储数据。 在存储元件上提供布线。

公开(公告)号：US20110068404A1

公开(公告)日：2011-03-24

申请号：US12726300

申请日：2010-03-17

申请人： Kuniaki SUGIURA ,  Takeshi KAJIYAMA ,  Yoshiaki ASAO

发明人： Kuniaki SUGIURA ,  Takeshi KAJIYAMA ,  Yoshiaki ASAO

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

摘要： A semiconductor device includes a first semiconductor layer and a second semiconductor layer that have a form of fins and are arranged a predetermined distance apart from each other, in which a center portion of each serves as a channel region, and side portions sandwiching the center portion serve as source/drain regions, a gate electrode formed on two side surfaces of each of the channel regions of the first semiconductor layer and the second semiconductor layer, with a gate insulating film interposed therebetween, an insulating film formed to fill a gap between the source/drain regions of the first semiconductor layer and the source/drain regions of the second semiconductor layer, and silicide layers formed on side surfaces of the source/drain regions of the first semiconductor layer and the source/drain regions of the second semiconductor layer that are not covered by the insulating film.

摘要翻译： 半导体器件包括第一半导体层和第二半导体层，该第一半导体层和第二半导体层具有散热片的形式并且彼此隔开预定距离，其中每个半导体层的中心部分用作沟道区域;以及侧部分夹着中心部分 作为源极/漏极区域，形成在第一半导体层和第二半导体层的每个沟道区域的两个侧面上的栅电极，隔着栅极绝缘膜，形成为填充第二半导体层之间的间隙的绝缘膜 第一半导体层的源极/漏极区域和第二半导体层的源极/漏极区域以及形成在第一半导体层的源极/漏极区域和第二半导体层的源极/漏极区域的侧表面上的硅化物层 不被绝缘膜覆盖。