公开(公告)号：US20100078763A1

公开(公告)日：2010-04-01

申请号：US12559446

申请日：2009-09-14

申请人： Keiji HOSOTANI ,  Yoshiaki ASAO ,  Kuniaki SUGIURA ,  Masatoshi YOSHIKAWA ,  Sumio IKEGAWA ,  Shigeki TAKAHASHI ,  Minoru AMANO

发明人： Keiji HOSOTANI ,  Yoshiaki ASAO ,  Kuniaki SUGIURA ,  Masatoshi YOSHIKAWA ,  Sumio IKEGAWA ,  Shigeki TAKAHASHI ,  Minoru AMANO

IPC分类号： H01L29/86 ,  H01L21/8239

CPC分类号： H01L43/08 ,  G11C11/161

摘要： A resistance-change memory includes an interlayer insulating film, a lower electrode layer, a fixed layer, a first insulating film, a recording layer, a second insulating film, a conducting layer and an interconnect. The interlayer insulating film is formed on a semiconductor substrate and has a step. The lower electrode layer is formed on the interlayer insulating film including the step. The fixed layer is formed on the lower electrode layer and has invariable magnetization. The first insulating film is formed on the fixed layer. The recording layer is formed on part of the first insulating film and has variable magnetization. The second insulating film is over the recording layer and in contact with the first insulating film. The conducting layer is formed on the second insulating film. The interconnect is connected to the conducting layer.

摘要翻译： 电阻变化存储器包括层间绝缘膜，下电极层，固定层，第一绝缘膜，记录层，第二绝缘膜，导电层和互连。 层间绝缘膜形成在半导体基板上并具有台阶。 包括该步骤的层间绝缘膜上形成下电极层。 固定层形成在下电极层上，具有不变的磁化。 第一绝缘膜形成在固定层上。 记录层形成在第一绝缘膜的一部分上并且具有可变的磁化强度。 第二绝缘膜在记录层上方并与第一绝缘膜接触。 导电层形成在第二绝缘膜上。 互连连接到导电层。

公开(公告)号：US20100197044A1

公开(公告)日：2010-08-05

申请号：US12699721

申请日：2010-02-03

申请人： Takeshi KAJIYAMA ,  Yoshiaki ASAO ,  Minoru AMANO ,  Shigeki TAKAHASHI ,  Masayoshi IWAYAMA ,  Kuniaki SUGIURA

发明人： Takeshi KAJIYAMA ,  Yoshiaki ASAO ,  Minoru AMANO ,  Shigeki TAKAHASHI ,  Masayoshi IWAYAMA ,  Kuniaki SUGIURA

IPC分类号： H01L21/28 ,  B28B17/00

CPC分类号： H01L43/12 ,  G11C11/161 ,  H01L27/228

摘要： A magnetic material of a magnetoresistive element is formed on a lower electrode. An upper electrode is formed on the magnetic material. A resist for nano-imprint lithography is formed on the upper electrode. A first pattern or a second pattern is formed in the resist by setting a first template or a second template into contact with the resist and curing the resist. The first template has the first pattern that corresponds to the magnetoresistive element and the lower electrode. The second template has the second pattern that corresponds to the magnetoresistive element and the upper electrode. The magnetic material and the lower electrode are patterned at the same time by using the resist having the first pattern, or the magnetic material and the upper electrode are patterned at the same time by using the resist having the second pattern.

摘要翻译： 磁阻元件的磁性材料形成在下电极上。 在磁性材料上形成上部电极。 在上电极上形成用于纳米压印光刻的抗蚀剂。 通过将第一模板或第二模板与抗蚀剂接触并固化抗蚀剂，在抗蚀剂中形成第一图案或第二图案。 第一模板具有对应于磁阻元件和下电极的第一图案。 第二模板具有对应于磁阻元件和上电极的第二图案。 通过使用具有第一图案的抗蚀剂，同时对磁性材料和下电极进行图案化，或者通过使用具有第二图案的抗蚀剂同时对磁性材料和上部电极进行图案化。

公开(公告)号：US20110254112A1

公开(公告)日：2011-10-20

申请号：US13015410

申请日：2011-01-27

申请人： Takaya YAMANAKA ,  Yoshiaki ASAO ,  Takeshi KAJIYAMA ,  Minoru AMANO ,  Masayoshi IWAYAMA ,  Kuniaki SUGIURA ,  Yukinori KOYAMA

发明人： Takaya YAMANAKA ,  Yoshiaki ASAO ,  Takeshi KAJIYAMA ,  Minoru AMANO ,  Masayoshi IWAYAMA ,  Kuniaki SUGIURA ,  Yukinori KOYAMA

IPC分类号： H01L29/82 ,  H01L21/4763

CPC分类号： H01L27/228 ,  H01L21/7684 ,  H01L43/12

摘要： A semiconductor memory device includes a semiconductor substrate, and plural switching transistors provided on the semiconductor substrate. A contact plug is embedded between the adjacent two switching transistors described above, is insulated from gates of the adjacent two switching transistors, and is electrically connected to diffusion layers of the adjacent two switching transistors. An upper connector is formed on the contact plug, and an upper surface is at a position higher than upper surfaces of the switching transistors. A memory element is provided on the upper surface of the upper connector, and stores data. A wiring is provided on the memory element.

摘要翻译： 半导体存储器件包括半导体衬底和设置在半导体衬底上的多个开关晶体管。 接触插头嵌入在上述相邻的两个开关晶体管之间，与相邻的两个开关晶体管的栅极绝缘，并且电连接到相邻的两个开关晶体管的扩散层。 在接触插塞上形成上连接器，上表面位于高于开关晶体管的上表面的位置。 存储元件设置在上连接器的上表面上并存储数据。 在存储元件上提供布线。

公开(公告)号：US20110215382A1

公开(公告)日：2011-09-08

申请号：US13035168

申请日：2011-02-25

申请人： Yoshiaki ASAO ,  Takeshi KAJIYAMA ,  Kuniaki SUGIURA

发明人： Yoshiaki ASAO ,  Takeshi KAJIYAMA ,  Kuniaki SUGIURA

IPC分类号： H01L29/82

CPC分类号： H01L29/82

摘要： According to one embodiment, a semiconductor memory device is disclosed. The device includes MOSFET1 and MOSFET2 arranged in a first direction, variable resistive element (hereafter R1) above MOSFET1 and MOSFET2, a lower end of the R1 being connected to drains of MOSFET1 and MOSFET2, MOSFET3 and MOSFET4 arranged in the first direction, variable resistive element (hereafter R2) above MOSFET3 and MOSFET4, and a lower end of the R2 being connected to drains of MOSFET3 and MOSFET4. The device further includes first wiring line extending in the first direction and connected to sources of MOSFET1 and MOSFET2, second wiring line extending in the first direction and connected to sources of MOSFET3 and MOSFET4, upper electrode connecting upper end of the R1 and upper end of the R2, and third wiring line extending in the first direction and connected to the upper electrode.

摘要翻译： 根据一个实施例，公开了一种半导体存储器件。 该器件包括在第一方向上布置的MOSFET1和MOSFET2，MOSFET1和MOSFET2上方的可变电阻元件（以下称为R1），R1的下端连接到沿第一方向布置的MOSFET1和MOSFET2，MOSFET3和MOSFET4的漏极，可变电阻 元件（以下称为R2），MOSFET3和MOSFET4之上，R2的下端连接到MOSFET3和MOSFET4的漏极。 该器件还包括沿第一方向延伸并连接到MOSFET1和MOSFET2的源极的第一布线，第二布线沿第一方向延伸并连接到MOSFET3和MOSFET4的源极，上电极连接R1的上端和上端 R2和第三布线沿第一方向延伸并连接到上电极。

公开(公告)号：US20110037108A1

公开(公告)日：2011-02-17

申请号：US12854724

申请日：2010-08-11

申请人： Kuniaki SUGIURA ,  Yoshiaki ASAO ,  Takeshi KAJIYAMA

发明人： Kuniaki SUGIURA ,  Yoshiaki ASAO ,  Takeshi KAJIYAMA

IPC分类号： H01L29/82 ,  H01L21/02

CPC分类号： H01L27/228 ,  H01L43/08 ,  H01L43/12

摘要： According to one embodiment, a magnetoresistive memory includes first and second contact plugs in a first interlayer insulating film, a lower electrode on the first interlayer insulating film, a magnetoresistive effect element on the lower electrode, and an upper electrode on the magnetoresistive effect element. The lower electrode has a tapered cross-sectional shape in which a dimension of a bottom surface of the lower electrode is longer than a dimension of an upper surface of the lower electrode, one end of the lower electrode is in contact with an upper surface of the first contact plug. The magnetoresistive effect element is provided at a position shifted from a position immediately above the first contact plug in a direction parallel to a surface of the semiconductor substrate.

摘要翻译： 根据一个实施例，磁阻存储器包括第一层间绝缘膜中的第一和第二接触插塞，第一层间绝缘膜上的下电极，下电极上的磁阻效应元件和磁阻效应元件上的上电极。 下电极具有锥形横截面形状，其中下电极的底表面的尺寸比下电极的上表面的尺寸长，下电极的一端与上电极的上表面接触 第一个接触插头。 磁阻效应元件设置在与第一接触插塞正上方的位置在平行于半导体衬底的表面的方向上偏移的位置处。

公开(公告)号：US20110068404A1

公开(公告)日：2011-03-24

申请号：US12726300

申请日：2010-03-17

申请人： Kuniaki SUGIURA ,  Takeshi KAJIYAMA ,  Yoshiaki ASAO

发明人： Kuniaki SUGIURA ,  Takeshi KAJIYAMA ,  Yoshiaki ASAO

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

摘要： A semiconductor device includes a first semiconductor layer and a second semiconductor layer that have a form of fins and are arranged a predetermined distance apart from each other, in which a center portion of each serves as a channel region, and side portions sandwiching the center portion serve as source/drain regions, a gate electrode formed on two side surfaces of each of the channel regions of the first semiconductor layer and the second semiconductor layer, with a gate insulating film interposed therebetween, an insulating film formed to fill a gap between the source/drain regions of the first semiconductor layer and the source/drain regions of the second semiconductor layer, and silicide layers formed on side surfaces of the source/drain regions of the first semiconductor layer and the source/drain regions of the second semiconductor layer that are not covered by the insulating film.

摘要翻译： 半导体器件包括第一半导体层和第二半导体层，该第一半导体层和第二半导体层具有散热片的形式并且彼此隔开预定距离，其中每个半导体层的中心部分用作沟道区域;以及侧部分夹着中心部分 作为源极/漏极区域，形成在第一半导体层和第二半导体层的每个沟道区域的两个侧面上的栅电极，隔着栅极绝缘膜，形成为填充第二半导体层之间的间隙的绝缘膜 第一半导体层的源极/漏极区域和第二半导体层的源极/漏极区域以及形成在第一半导体层的源极/漏极区域和第二半导体层的源极/漏极区域的侧表面上的硅化物层 不被绝缘膜覆盖。

公开(公告)号：US20100193850A1

公开(公告)日：2010-08-05

申请号：US12697912

申请日：2010-02-01

申请人： Yoshiaki ASAO ,  Takeshi KAJIYAMA ,  Minoru AMANO ,  Yoshikuni TATEYAMA ,  Atsushi SHIGETA

发明人： Yoshiaki ASAO ,  Takeshi KAJIYAMA ,  Minoru AMANO ,  Yoshikuni TATEYAMA ,  Atsushi SHIGETA

IPC分类号： H01L29/82

CPC分类号： H01L27/228 ,  H01L27/105

摘要： First and second transistors are formed on a substrate. An interlayer insulating film is formed on the first transistor. A first contact is formed in the interlayer film on a source or a drain of the first transistor. A second contact is formed in the interlayer film on the other of the source or the drain. A first interconnect is formed on the first contact. A magnetoresistive element is formed on the second contact. The magnetoresistive element is arranged in a layer having a height equal to that of the first interconnect from a substrate surface. A third contact is formed in the interlayer film on a source or a drain of the second transistor. A second interconnect is formed on the third contact. The second interconnect is arranged in a layer having a height equal to those of the first interconnect and the magnetoresistive element from the substrate surface.

摘要翻译： 第一和第二晶体管形成在衬底上。 在第一晶体管上形成层间绝缘膜。 在第一晶体管的源极或漏极上的层间膜中形成第一接触。 在源极或漏极中的另一个的层间膜中形成第二接触。 在第一接触件上形成第一互连。 在第二触点上形成磁阻元件。 磁阻元件从衬底表面布置成具有与第一互连的高度相同的高度的层。 在第二晶体管的源极或漏极上的层间膜中形成第三接触。 在第三触点上形成第二互连。 第二互连布置在具有与来自衬底表面的第一互连和磁阻元件的高度相同的高度的层中。

公开(公告)号：US20140284738A1

公开(公告)日：2014-09-25

申请号：US14018337

申请日：2013-09-04

申请人： Takashi NAKAZAWA ,  Yoshiaki ASAO ,  Takeshi KAJIYAMA ,  Kenji NOMA

发明人： Takashi NAKAZAWA ,  Yoshiaki ASAO ,  Takeshi KAJIYAMA ,  Kenji NOMA

IPC分类号： H01L43/02 ,  H01L43/12

CPC分类号： H01L27/228 ,  G11C11/161 ,  G11C11/1655 ,  H01L27/2463 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

摘要： According to one embodiment, a magnetic memory including an isolation region with an insulator in a trench is disclosed. The isolation region defines active areas extending in a 1st direction and having 1st and 2nd active areas, an isolation region extending in a 2nd direction perpendicular to the 1st direction exists between the 1st and 2nd active areas. 1st and 2nd word lines extending in the 2nd direction are buried in a surface of semiconductor substrate. 1st and 2nd select transistors connected to the word lines are on the 1st active area. 1st and 2nd variable resistance elements connected to drain regions of the 1st and 2nd select transistors are on the 1st active area.

摘要翻译： 根据一个实施例，公开了一种包括在沟槽中具有绝缘体的隔离区的磁存储器。 隔离区域限定在第一方向上延伸并且具有第一和第二有源区域的有源区域，在第一和第二有效区域之间存在沿垂直于第一方向的第二方向延伸的隔离区域。 在第二方向上延伸的第一和第二字线被埋在半导体衬底的表面中。 连接到字线的第一和第二选择晶体管在第一有效区域。 连接到第一和第二选择晶体管的漏极区的第一和第二可变电阻元件在第一有效区上。

公开(公告)号：US20140284533A1

公开(公告)日：2014-09-25

申请号：US13963710

申请日：2013-08-09

申请人： Yoshiaki ASAO ,  Hideaki HARAKAWA

发明人： Yoshiaki ASAO ,  Hideaki HARAKAWA

IPC分类号： H01L43/02

CPC分类号： H01L27/228 ,  G11C11/161 ,  G11C11/165 ,  G11C11/1675 ,  H01L43/08

摘要： According to one embodiment, a semiconductor memory device comprises a cell transistor includes a first gate electrode buried in a semiconductor substrate and a first diffusion layer and a second diffusion layer formed to sandwich the first gate electrode, a first lower electrode formed on the first diffusion layer, a magnetoresistive element formed on the first lower electrode to store data according to a change in a magnetization state and connected to a bit line located above, a second lower electrode formed on the second diffusion layer, and a first contact formed on the second lower electrode and connected to a source line located above. A contact area between the second lower electrode and the second diffusion layer is larger than a contact area between the first contact and the second lower electrode.

摘要翻译： 根据一个实施例，一种半导体存储器件包括：单元晶体管，包括埋在半导体衬底中的第一栅电极和形成为夹着第一栅电极的第一扩散层和第二扩散层;形成在第一扩散层上的第一下电极 层，形成在所述第一下电极上以根据磁化状态的变化存储数据并连接到位于上方的位线的磁阻元件，形成在所述第二扩散层上的第二下电极，以及形成在所述第二扩散层上的第一触点 下电极并连接到位于上方的源极线。 第二下部电极和第二扩散层之间的接触面积大于第一接触部和第二下部电极的接触面积。

公开(公告)号：US20080239782A1

公开(公告)日：2008-10-02

申请号：US11861878

申请日：2007-09-26

申请人： Yoshiaki ASAO

发明人： Yoshiaki ASAO

IPC分类号： G11C5/02

CPC分类号： G11C5/025 ,  H01L27/228

摘要： A semiconductor memory device includes a bit line which is provided above a semiconductor substrate and runs in a first direction, a source line which is provided above the semiconductor substrate and runs in the first direction, an active area which is provided in the semiconductor substrate and extends in the first direction, first and second selection transistors which are formed on the active area and share a source region electrically connected to the source line, a first memory element having one end electrically connected to a drain region of the first selection transistor and the other end electrically connected to the bit line, and a second memory element having one end electrically connected to a drain region of the second selection transistor and the other end electrically connected to the bit line.

摘要翻译： 一种半导体存储器件，包括设置在半导体衬底上并沿第一方向延伸的位线，设置在半导体衬底上并沿第一方向延伸的源极线，设置在半导体衬底中的有源区和 在第一方向延伸，第一和第二选择晶体管，其形成在有源区上并共享与源极线电连接的源极区;第一存储元件，其一端电连接到第一选择晶体管的漏极区， 另一端电连接到位线，以及第二存储元件，其一端电连接到第二选择晶体管的漏极区域，另一端电连接到位线。