公开(公告)号：US6005422A

公开(公告)日：1999-12-21

申请号：US773313

申请日：1996-12-24

申请人： Hiroyuki Morinaka ,  Hiroshi Makino ,  Kimio Ueda ,  Koichiro Mashiko

发明人： Hiroyuki Morinaka ,  Hiroshi Makino ,  Kimio Ueda ,  Koichiro Mashiko

IPC分类号： G06F13/38 ,  G06F1/32 ,  G06F5/00 ,  H03K19/00 ,  H04L25/02 ,  H03K1/04 ,  G06F1/08

CPC分类号： G06F7/523 ,  G06F1/32 ,  G06F5/00 ,  H03K19/0008

摘要： A semiconductor integrated circuit and a method for reducing the consumed power are provided. A comparator outputs bits having the same level, which correspond to each other, of a last input stored in a register and a current input that acts as an input signal. A zero counter counts the number of the bits having the same level output from the comparator. If the number of the bits having the same level is smaller than a predetermined number, the current input is not similar to the last input. Consequently, an instruction is given to a flip-flop to invert the current input. The inverted current input becomes similar to the last input. Thus, the consumed power of a logic can be reduced.

摘要翻译： 提供半导体集成电路和降低功耗的方法。 比较器输出存储在寄存器中的最后一个输入和作为输入信号的当前输入的具有相同电平的位。 零计数器对比较器具有相同电平输出的位数进行计数。 如果具有相同电平的位的数量小于预定数量，则当前输入与最后一个输入不相似。 因此，给触发器指示反转当前输入。 反相电流输入变得与最后一个输入相似。 因此，可以减少逻辑的消耗功率。

公开(公告)号：US5891765A

公开(公告)日：1999-04-06

申请号：US782944

申请日：1997-01-13

申请人： Kimio Ueda ,  Hiroyuki Morinaka ,  Koichiro Mashiko

发明人： Kimio Ueda ,  Hiroyuki Morinaka ,  Koichiro Mashiko

IPC分类号： H01L21/82 ,  H01L21/84 ,  H01L27/118 ,  H01L27/12 ,  H01L29/786 ,  H01L27/01 ,  H01L27/10 ,  H01L29/76

CPC分类号： H01L21/84 ,  H01L27/118 ,  H01L27/11807 ,  H01L27/1203

摘要： In order to improve a withstand voltage and implement a gate array SOI semiconductor integrated circuit device having a large gate width, a region consisting of end cells (49) is provided on each end of a region formed by repeatedly arranging basic cells (BC) consisting of both transistor regions (32, 33) in a first direction and while symmetrically arranging the same to be folded in a second direction. Both ends of a channel region of a PMOS transistor (42) are drawn out in the second direction to provide a P-type semiconductor layer just under a field shielding gate electrode (FG), and this semiconductor layer is drawn also in the first direction to be connected with a P-type semiconductor layer of the end cell (49). A first source potential is applied to a region (PBD) which is bonded with one of the P-type semiconductor layers. Also as to an NMOS transistor (41) which is adjacent through a field oxide film (FO), on the other hand, an N-type semiconductor layer is similarly provided so that this N-type semiconductor layer is also connected with that of the end cell (49). A second source potential is applied to a region (NBD).

摘要翻译： 为了提高耐压并实现具有较大栅极宽度的栅阵列SOI半导体集成电路器件，在通过重复布置基本单元（BC）形成的区域的每个端部上设置由端单元（49）组成的区域，所述基本单元（BC） 的两个晶体管区域（32,33）在第一方向上并且同时对称地布置在第二方向上被折叠。 PMOS晶体管（42）的沟道区域的两端在第二方向上被拉出以提供刚好在场屏蔽栅极（FG）下面的P型半导体层，并且该半导体层也沿第一方向 与端电池（49）的P型半导体层连接。 将第一源极电位施加到与一个P型半导体层接合的区域（PBD）。 另一方面，与通过场氧化膜（FO）相邻的NMOS晶体管（41）也类似地设置N型半导体层，使得该N型半导体层也与 端单元（49）。 第二源电位被应用于区域（NBD）。

公开(公告)号：US5747847A

公开(公告)日：1998-05-05

申请号：US708269

申请日：1996-09-06

申请人： Hiroyuki Morinaka ,  Kimio Ueda ,  Koichiro Mashiko

发明人： Hiroyuki Morinaka ,  Kimio Ueda ,  Koichiro Mashiko

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/06 ,  H01L29/49 ,  H01L29/786 ,  H01L29/788

CPC分类号： H01L29/66651 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/4908 ,  H01L29/66772 ,  H01L29/78612 ,  H01L29/78645 ,  H01L29/78648

摘要： A semiconductor integrated circuit device having a SOI structure which can prevent a deterioration in the breakdown voltage of a transistor without damaging integration, and a method for manufacturing the semiconductor integrated circuit device are obtained. An embedded oxide film is not formed over the whole face of a P type silicon layer but has an opening in a region which is placed below a gate electrode. The opening is filled in to form a penetration P layer. Accordingly, a SOI layer is electrically connected to the P type silicon layer through the penetration P layer. The plane position and shape of the gate electrode conform to those of the penetration P layer.

摘要翻译： 具有能够防止晶体管的击穿电压劣化而不损害集成度的SOI结构的半导体集成电路器件，以及半导体集成电路器件的制造方法。 在P型硅层的整个表面上不形成嵌入的氧化物膜，但在位于栅电极下方的区域中具有开口。 填充开口以形成穿透P层。 因此，SOI层通过穿透P层与P型硅层电连接。 栅电极的平面位置和形状与穿透层P的平面位置和形状一致。

公开(公告)号：US5633524A

公开(公告)日：1997-05-27

申请号：US580609

申请日：1995-12-29

申请人： Kimio Ueda ,  Hiroyuki Morinaka ,  Koichiro Mashiko

发明人： Kimio Ueda ,  Hiroyuki Morinaka ,  Koichiro Mashiko

IPC分类号： H01L21/82 ,  H01L21/84 ,  H01L27/118 ,  H01L27/12 ,  H01L29/786 ,  H01L27/10 ,  H01L27/01 ,  H01L29/76

CPC分类号： H01L21/84 ,  H01L27/118 ,  H01L27/11807 ,  H01L27/1203

摘要： In order to improve a withstand voltage and implement a gate array SOI semiconductor integrated circuit device having a large gate width, a region consisting of end cells (49) is provided on each end of a region formed by repeatedly arranging basic cells (BC) consisting of both transistor regions (32, 33) in a first direction and while symmetrically arranging the same to be folded in a second direction. Both ends of a channel region of a PMOS transistor (42) are drawn out in the second direction to provide a P-type semiconductor layer just under a field shielding gate electrode (FG), and this semiconductor layer is drawn also in the first direction to be connected with a P-type semiconductor layer of the end cell (49). A first source potential is applied to a region (PBD) which is bonded with one of the P-type semiconductor layers. Also as to an NMOS transistor (41) which is adjacent through a field oxide film (FO), on the other hand, an N-type semiconductor layer is similarly provided so that this N-type semiconductor layer is also connected with that of the end cell (49). A second source potential is applied to a region (NBD).

摘要翻译： 为了提高耐压并实现具有较大栅极宽度的栅阵列SOI半导体集成电路器件，在通过重复布置基本单元（BC）形成的区域的每个端部上设置由端单元（49）组成的区域，所述基本单元（BC） 的两个晶体管区域（32,33）在第一方向上并且同时对称地布置在第二方向上被折叠。 PMOS晶体管（42）的沟道区域的两端在第二方向上被拉出以提供刚好在场屏蔽栅极（FG）下面的P型半导体层，并且该半导体层也沿第一方向 与端电池（49）的P型半导体层连接。 将第一源极电位施加到与一个P型半导体层接合的区域（PBD）。 另一方面，与通过场氧化膜（FO）相邻的NMOS晶体管（41）也类似地设置N型半导体层，使得该N型半导体层也与 端单元（49）。 第二源电位被应用于区域（NBD）。

公开(公告)号：US5859800A

公开(公告)日：1999-01-12

申请号：US949821

申请日：1997-10-14

申请人： Kimio Ueda ,  Hiroyuki Morinaka ,  Koichiro Mashiko

发明人： Kimio Ueda ,  Hiroyuki Morinaka ,  Koichiro Mashiko

IPC分类号： H03K3/356 ,  G11C7/10 ,  H03K3/037 ,  H03K19/00 ,  G11C7/00

CPC分类号： G11C7/1051 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/1093 ,  H03K3/356121 ,  H03K3/356173

摘要： A highly reliable data holding circuit with a reduced circuit area and reduced power consumption is disclosed. Output terminals (DO, DOB) are connected to input terminals (DI, DIB) receiving signals at H and L levels (potentials VDD and GND) in mutually exclusive relation through transistors (MN2, MN1) and inverters (INV1, INV2). Input terminals of the inverters (INV1, INV2) are connected to power supplies (VDD) through transistors (MP2, MP1) having gate electrodes connected to output terminals of the inverters (INV2, INV1), respectively. The transistors (MN2, MN1) cause a voltage drop of the signals to be applied to the inverters (INV1, INV2) by the amount of a threshold voltage (Vthn). One of the transistors (MP1, MP2) which receives a signal at L level at its control terminal provides a potential (VDD) to the input terminal of one of the inverters (INV1, INV2) which is to output a signal at L level, compensating for the voltage drop by the amount of the threshold voltage (Vthn).

摘要翻译： 公开了一种具有降低的电路面积和降低的功耗的高度可靠的数据保持电路。 输出端子（DO，DOB）通过晶体管（MN2，MN1）和反相器（INV1，INV2）以H和L电平（电位VDD和GND）的互斥关系连接到输入端子（DI，DIB）。 反相器（INV1，INV2）的输入端分别通过连接到反相器（INV2，INV1）的输出端的栅电极的晶体管（MP2，MP1）连接到电源（VDD）。 晶体管（MN2，MN1）使信号的电压降到施加到反相器（INV1，INV2）的量的阈值电压（Vthn）。 在其控制端子处接收到L电平的信号的晶体管（MP1，MP2）中的一个为向L电平输出信号的反相器（INV1，INV2）中的一个的输入端提供电位（VDD） 通过阈值电压（Vthn）的量来补偿电压降。

公开(公告)号：US5781062A

公开(公告)日：1998-07-14

申请号：US582416

申请日：1996-01-03

申请人： Koichiro Mashiko ,  Kimio Ueda ,  Hiroaki Suzuki ,  Hiroyuki Morinaka

发明人： Koichiro Mashiko ,  Kimio Ueda ,  Hiroaki Suzuki ,  Hiroyuki Morinaka

IPC分类号： G11C5/14 ,  G11C11/407 ,  H03K19/00 ,  H03K19/0948 ,  G05F1/10

CPC分类号： H03K19/0016 ,  G11C5/14 ,  G11C5/147 ,  H01L2924/0002

摘要： A logic circuit (L.sub.i) is connected between a virtual power supply line (VDDV) connected to an actual power supply (VDD) through a PMOS transistor (Q1) and a virtual grounding line (GNDV) connected to an actual ground (GND) through an NMOS transistor (Q2). During an active period, the transistors (Q1, Q2) are constantly conducting, and the virtual power supply line (VDDV) and virtual grounding line (GNDV) are at the power supply potential (VDD) and ground potential (GND), respectively. During a standby period, the transistors (Q1, Q2) periodically repeat conduction/non-conduction to charge and discharge the virtual power supply line (VDDV) and virtual grounding line (GNDV), suppressing power consumption while preventing loss of information held by the logic circuit (L.sub.i).

摘要翻译： 逻辑电路（Li）通过PMOS晶体管（Q1）连接到与实际电源（VDD）连接的虚拟电源线（VDDV）和连接到实际地线（GND）的虚拟接地线（GNDV）之间通过 一个NMOS晶体管（Q2）。 在激活期间，晶体管（Q1，Q2）恒定导通，虚拟电源线（VDDV）和虚拟接地线（GNDV）分别处于电源电位（VDD）和接地电位（GND）。 在待机期间，晶体管（Q1，Q2）周期性地重复导通/非导通，对虚拟电源线（VDDV）和虚拟接地线（GNDV）进行充电和放电，从而抑制功耗，同时防止由 逻辑电路（Li）。

公开(公告)号：US06177826B1

公开(公告)日：2001-01-23

申请号：US09053700

申请日：1998-04-02

申请人： Koichiro Mashiko ,  Kimio Ueda ,  Yoshiki Wada

发明人： Koichiro Mashiko ,  Kimio Ueda ,  Yoshiki Wada

IPC分类号： H03K190948

CPC分类号： H03K19/0027 ,  H03K19/01707 ,  H03K2217/0018

摘要： A Silicon-On-Insulator (SOI) CMOS circuit comprises a plurality of PMOS transistors connected in series to each other, each of the plurality of PMOS transistors having its body and gate connected to each other, and at least an NMOS transistor connected to one of the plurality of PMOS transistors, the NMOS transistor having its body connected to a low reference potential having a value of ground. The SOI CMOS circuit can further comprise a plurality of potential limiting circuits each connected between the body and gate of each of the plurality of PMOS transistors, for setting a lower limit of the potential of the body of each of the plurality of PMOS transistors to a voltage between a high reference potential and a potential obtained by subtracting a built-in potential from the high reference potential.

摘要翻译： 绝缘体上硅绝缘体（SOI）CMOS电路包括彼此串联连接的多个PMOS晶体管，多个PMOS晶体管中的每一个具有彼此连接的主体和栅极，以及连接到一个的至少一个NMOS晶体管 的NMOS晶体管，其NMOS晶体管的主体连接到具有接地值的低参考电位。 SOI CMOS电路还可以包括多个限制电路，每个电位限制电路连接在多个PMOS晶体管中的每一个的主体和栅极之间，用于将多个PMOS晶体管的每个的主体的电位的下限设置为 通过从高参考电位减去内置电位而获得的高参考电位和电位之间的电压。

公开(公告)号：US5994935A

公开(公告)日：1999-11-30

申请号：US130607

申请日：1998-08-07

申请人： Kimio Ueda ,  Koichiro Mashiko ,  Yoshiki Wada

发明人： Kimio Ueda ,  Koichiro Mashiko ,  Yoshiki Wada

IPC分类号： H03K3/037 ,  H03K3/356 ,  H03K3/3562

CPC分类号： H03K3/35625 ,  H03K3/356156

摘要： A flip-flop circuit is constituted of two latch circuits of the same structure that are cascaded. The latch circuits each includes an inverter formed of a P channel transistor and an N channel transistor, an N channel transistor connected between a common node and a ground node, and two data input/output terminals. Two kinds of clock signals supplied to gates of N channel transistors are complementary to each other.

摘要翻译： 触发器电路由级联的相同结构的两个锁存电路构成。 锁存电路各自包括由P沟道晶体管和N沟道晶体管形成的反相器，连接在公共节点和接地节点之间的N沟道晶体管，以及两个数据输入/输出端子。 提供给N沟道晶体管的栅极的两种时钟信号彼此互补。

公开(公告)号：US06433620B1

公开(公告)日：2002-08-13

申请号：US09716260

申请日：2000-11-21

申请人： Koichiro Mashiko ,  Kimio Ueda ,  Yoshiki Wada

发明人： Koichiro Mashiko ,  Kimio Ueda ,  Yoshiki Wada

IPC分类号： H03K190948

CPC分类号： H03K19/0027 ,  H03K19/01707 ,  H03K2217/0018

摘要： A Silicon-On-Insulator (SOI) CMOS circuit includes a plurality of PMOS transistors connected in series to each other and at least one NMOS transistor connected to one of the PMOS transistors. The NMOS transistor has its body connected to a low reference potential having a value of ground. The SOI CMOS circuit further includes a body potential generating circuit which generates a body potential between a high reference potential and a potential obtained by subtracting a built-in potential from the high reference potential. The body potential generating circuit applies the high potential to the bodies of the PMOS transistors.

摘要翻译： 绝缘体上硅绝缘体（SOI）CMOS电路包括彼此串联连接的多个PMOS晶体管和连接到PMOS晶体管之一的至少一个NMOS晶体管。 NMOS晶体管的主体连接到具有接地值的低参考电位。 SOI CMOS电路还包括体电位发生电路，其产生高参考电位和通过从高参考电位减去内置电位而获得的电位之间的体电位。 体电位产生电路将高电位施加到PMOS晶体管的主体。

公开(公告)号：US06242786B1

公开(公告)日：2001-06-05

申请号：US09213280

申请日：1998-12-17

申请人： Yoshiki Wada ,  Hirotada Kuriyama ,  Kimio Ueda ,  Koichiro Mashiko ,  Hiroaki Suzuki

发明人： Yoshiki Wada ,  Hirotada Kuriyama ,  Kimio Ueda ,  Koichiro Mashiko ,  Hiroaki Suzuki

IPC分类号： H01L2940

CPC分类号： H01L21/76264 ,  H01L21/76291 ,  H01L27/1203

摘要： A field shield portion consisting of a kind of transistor is formed to electrically insulate an NMOS region of a memory cell from other regions. The field shield portion includes a field shield gate electrode layer, a p type region and a gate insulating film. Threshold value of this transistor is set higher than the power supply voltage, and field gate electrode layer thereof is in a floating state. It is unnecessary to provide a contact portion for applying a prescribed voltage at field shield gate electrode layer. Therefore, the region for forming the contact portion in field shield gate electrode layer can be reduced. As a result, a semiconductor device of which layout area is reduced, is provided.

摘要翻译： 形成由一种晶体管组成的场屏蔽部分，以将存储器单元的NMOS区域与其他区域电绝缘。 场屏蔽部分包括场屏蔽栅极电极层，p型区域和栅极绝缘膜。 该晶体管的阈值被设定为高于电源电压，并且其栅极电极层处于浮置状态。 不需要在场屏蔽栅电极层设置用于施加规定电压的接触部。 因此，可以减小在场屏蔽栅电极层中形成接触部分的区域。 结果，提供了一种其布局面积减小的半导体器件。