公开(公告)号：US08004044B2

公开(公告)日：2011-08-23

申请号：US12473710

申请日：2009-05-28

申请人： Hisashi Ogawa ,  Yoshihiro Mori

发明人： Hisashi Ogawa ,  Yoshihiro Mori

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： H01L21/28088 ,  H01L21/823842 ,  H01L21/82385 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor device including a first transistor of a first conductivity type provided on a first active region of a semiconductor region, and a second transistor of a second conductivity type provided on a second active region of the semiconductor region. The first transistor includes a first gate insulating film and a first gate electrode, the first gate insulating film contains a high-k material and a first metal, and the first gate electrode includes a lower conductive film, a first conductive film and a first silicon film. The second transistor includes a second gate insulating film and a second gate electrode, the second gate insulating film contains a high-k material and a second metal, and the second gate electrode includes a second conductive film made of the same material as the first conductive film, and a second silicon film.

摘要翻译： 一种半导体器件，包括设置在半导体区域的第一有源区上的第一导电类型的第一晶体管和设置在半导体区域的第二有源区上的第二导电类型的第二晶体管。 第一晶体管包括第一栅极绝缘膜和第一栅电极，第一栅极绝缘膜包含高k材料和第一金属，并且第一栅电极包括下导电膜，第一导电膜和第一硅 电影。 第二晶体管包括第二栅极绝缘膜和第二栅电极，第二栅极绝缘膜包含高k材料和第二金属，第二栅极包括由与第一导电性材料相同的材料制成的第二导电膜 膜和第二硅膜。

公开(公告)号：US06974987B2

公开(公告)日：2005-12-13

申请号：US10477924

申请日：2003-02-14

申请人： Hisashi Ogawa ,  Isao Miyanaga ,  Koji Eriguchi ,  Takayuki Yamada ,  Kazuichiro Itonaga ,  Yoshihiro Mori

发明人： Hisashi Ogawa ,  Isao Miyanaga ,  Koji Eriguchi ,  Takayuki Yamada ,  Kazuichiro Itonaga ,  Yoshihiro Mori

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10882 ,  H01L27/10829 ,  H01L27/10894 ,  Y10S257/905 ,  Y10S257/908

摘要： A memory cell transistor and a trench capacitor are provided in a memory region, and both transistors of CMOS are provided in a logic circuit region. There are provided a bit line contact 31 and a bit line 32 extending on an inter-level dielectric 30. In a memory cell transistor, a source diffusion layer 18 is covered with two dielectric sidewalls 25a and 25b in the memory cell transistor so that no silicide layer is formed on the source diffusion layer 18. A plate contact 31 is provided to pass through the inter-level dielectric 30 and connect a shield line 33 to a plate electrode 16b. The shield line 33 is arranged in the same interconnect layer as the bit line 32.

摘要翻译： 存储单元晶体管和沟槽电容器设置在存储区域中，CMOS的两个晶体管都设置在逻辑电路区域中。 提供了位线接触件31和在层间电介质30上延伸的位线32。 在存储单元晶体管中，源极扩散层18被存储单元晶体管中的两个电介质侧壁25a和25b覆盖，使得在源极扩散层18上不形成硅化物层。 提供板触点31以通过层间电介质30并将屏蔽线33连接到平板电极16b。 屏蔽线33布置在与位线32相同的互连层中。

公开(公告)号：US06916705B2

公开(公告)日：2005-07-12

申请号：US10656153

申请日：2003-09-08

申请人： Hisashi Ogawa ,  Yoshihiro Mori ,  Akihiko Tsuzumitani

发明人： Hisashi Ogawa ,  Yoshihiro Mori ,  Akihiko Tsuzumitani

IPC分类号： H01L27/108 ,  H01L21/02 ,  H01L21/8242

CPC分类号： H01L27/10852 ,  H01L27/10894 ,  H01L28/55 ,  Y10S438/926

摘要： In a memory cell of a DRAM, that is, a semiconductor memory, a bit line connected to a bit line plug and a local interconnect are provided on a first interlayer insulating film. A connection conductor film of TiAlN is provided on the top and side faces of an upper barrier metal and side faces of a Pt film and a BST film. No contact is formed above the Pt film used for forming an upper electrode, and the upper electrode is connected to an upper interconnect (namely, a Cu interconnect) through the connection conductor film, a dummy lower electrode, a dummy cell plug and the local interconnect. Since the Pt film is not exposed to a reducing atmosphere, the characteristic degradation of a capacitor insulating film can be prevented.

摘要翻译： 在第一层间绝缘膜上设置DRAM的存储单元，即半导体存储器，连接到位线插头和局部互连的位线。 TiAlN的连接导体膜设置在上阻挡金属的顶面和侧面以及Pt膜和BST膜的侧面上。 在用于形成上电极的Pt膜上方没有形成接触，并且上电极通过连接导体膜，虚拟下电极，虚拟电池插头和本地连接到上互连（即Cu互连） 互连。 由于Pt膜没有暴露于还原气氛中，所以可以防止电容器绝缘膜的特性劣化。

公开(公告)号：US06642564B2

公开(公告)日：2003-11-04

申请号：US10196229

申请日：2002-07-17

申请人： Hisashi Ogawa ,  Yoshihiro Mori ,  Akihiko Tsuzumitani

发明人： Hisashi Ogawa ,  Yoshihiro Mori ,  Akihiko Tsuzumitani

IPC分类号： H01L27108

CPC分类号： H01L27/10852 ,  H01L27/10894 ,  H01L28/55 ,  Y10S438/926

摘要： In a memory cell of a DRAM, that is, a semiconductor memory, a bit line connected to a bit line plug and a local interconnect are provided on a first interlayer insulating film. A connection conductor film of TiAlN is provided on the top and side faces of an upper barrier metal and side faces of a Pt film and a BST film. No contact is formed above the Pt film used for forming an upper electrode, and the upper electrode is connected to an upper interconnect (namely, a Cu interconnect) through the connection conductor film, a dummy lower electrode, a dummy cell plug and the local interconnect. Since the Pt film is not exposed to a reducing atmosphere, the characteristic degradation of a capacitor insulating film can be prevented.

摘要翻译： 在第一层间绝缘膜上设置DRAM的存储单元，即半导体存储器，连接到位线插头和局部互连的位线。 TiAlN的连接导体膜设置在上阻挡金属的顶面和侧面以及Pt膜和BST膜的侧面上。 在用于形成上电极的Pt膜上方没有形成接触，并且上电极通过连接导体膜，虚拟下电极，虚拟电池插头和本地连接到上互连（即Cu互连） 互连。 由于Pt膜没有暴露于还原气氛中，所以可以防止电容器绝缘膜的特性劣化。

公开(公告)号：US08258582B2

公开(公告)日：2012-09-04

申请号：US13182993

申请日：2011-07-14

申请人： Hisashi Ogawa ,  Yoshihiro Mori

发明人： Hisashi Ogawa ,  Yoshihiro Mori

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： H01L21/28088 ,  H01L21/823842 ,  H01L21/82385 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor device including a first transistor of a first conductivity type provided on a first active region of a semiconductor region, and a second transistor of a second conductivity type provided on a second active region of the semiconductor region. The first transistor includes a first gate insulating film and a first gate electrode, the first gate insulating film contains a high-k material and a first metal, and the first gate electrode includes a lower conductive film, a first conductive film and a first silicon film. The second transistor includes a second gate insulating film and a second gate electrode, the second gate insulating film contains a high-k material and a second metal, and the second gate electrode includes a second conductive film made of the same material as the first conductive film, and a second silicon film.

摘要翻译： 一种半导体器件，包括设置在半导体区域的第一有源区上的第一导电类型的第一晶体管和设置在半导体区域的第二有源区上的第二导电类型的第二晶体管。 第一晶体管包括第一栅极绝缘膜和第一栅电极，第一栅极绝缘膜包含高k材料和第一金属，并且第一栅电极包括下导电膜，第一导电膜和第一硅 电影。 第二晶体管包括第二栅极绝缘膜和第二栅电极，第二栅极绝缘膜包含高k材料和第二金属，第二栅极包括由与第一导电性材料相同的材料制成的第二导电膜 膜和第二硅膜。

公开(公告)号：US06784474B2

公开(公告)日：2004-08-31

申请号：US10203430

申请日：2002-08-08

申请人： Hisashi Ogawa ,  Yoshihiro Mori ,  Akihiko Tsuzumitani

发明人： Hisashi Ogawa ,  Yoshihiro Mori ,  Akihiko Tsuzumitani

IPC分类号： H01L2976

CPC分类号： H01L27/10894 ,  H01L27/10885 ,  H01L28/55 ,  H01L28/60 ,  Y10S257/905 ,  Y10S257/908

摘要： A memory cell in a DRAM, which is a semiconductor memory device, is provided with a bit line 21a connected to a bit line plug 20b and a local interconnect 21b, over a first interlevel insulating film 18. A conductor sidewall 40 of TiAlN is formed on side faces of hard mask 37, upper barrier metal 36, Pt film 35 and BST film 34. No contact hole is provided on the Pt film 35 constituting an upper electrode 35a. The upper electrode 35a is connected to an upper interconnect (a Cu interconnect 42) via the conductor sidewall 40, dummy lower electrode 33b, dummy cell plug 30 and local interconnect 21b. The Pt film 35 is not exposed to a reducing atmosphere, and therefore deterioration in characteristics of the capacitive insulating film 34a can be prevented.

摘要翻译： 作为半导体存储器件的DRAM中的存储单元在第一层间绝缘膜18上设置有连接到位线插头20b和局部互连21b的位线21a。形成TiAlN的导体侧壁40 在硬掩模37，上阻挡金属36，Pt膜35和BST膜34的侧面上。在构成上电极35a的Pt膜35上没有设置接触孔。 上电极35a经由导体侧壁40，虚拟下电极33b，虚设电池插塞30和局部互连21b与上互连（铜互连42）连接。 Pt膜35不暴露于还原气氛中，因此可以防止电容绝缘膜34a的特性劣化。

公开(公告)号：US20090309165A1

公开(公告)日：2009-12-17

申请号：US12473710

申请日：2009-05-28

申请人： Hisashi OGAWA ,  Yoshihiro Mori

发明人： Hisashi OGAWA ,  Yoshihiro Mori

IPC分类号： H01L27/092 ,  H01L21/28

CPC分类号： H01L21/28088 ,  H01L21/823842 ,  H01L21/82385 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor device including a first transistor of a first conductivity type provided on a first active region of a semiconductor region, and a second transistor of a second conductivity type provided on a second active region of the semiconductor region. The first transistor includes a first gate insulating film and a first gate electrode, the first gate insulating film contains a high-k material and a first metal, and the first gate electrode includes a lower conductive film, a first conductive film and a first silicon film. The second transistor includes a second gate insulating film and a second gate electrode, the second gate insulating film contains a high-k material and a second metal, and the second gate electrode includes a second conductive film made of the same material as the first conductive film, and a second silicon film.

摘要翻译： 一种半导体器件，包括设置在半导体区域的第一有源区上的第一导电类型的第一晶体管和设置在半导体区域的第二有源区上的第二导电类型的第二晶体管。 第一晶体管包括第一栅极绝缘膜和第一栅电极，第一栅极绝缘膜包含高k材料和第一金属，并且第一栅电极包括下导电膜，第一导电膜和第一硅 电影。 第二晶体管包括第二栅极绝缘膜和第二栅电极，第二栅极绝缘膜包含高k材料和第二金属，第二栅极包括由与第一导电性材料相同的材料制成的第二导电膜 膜和第二硅膜。

公开(公告)号：US20110266629A1

公开(公告)日：2011-11-03

申请号：US13182993

申请日：2011-07-14

申请人： Hisashi OGAWA ,  Yoshihiro Mori

发明人： Hisashi OGAWA ,  Yoshihiro Mori

IPC分类号： H01L27/092

CPC分类号： H01L21/28088 ,  H01L21/823842 ,  H01L21/82385 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor device including a first transistor of a first conductivity type provided on a first active region of a semiconductor region, and a second transistor of a second conductivity type provided on a second active region of the semiconductor region. The first transistor includes a first gate insulating film and a first gate electrode, the first gate insulating film contains a high-k material and a first metal, and the first gate electrode includes a lower conductive film, a first conductive film and a first silicon film. The second transistor includes a second gate insulating film and a second gate electrode, the second gate insulating film contains a high-k material and a second metal, and the second gate electrode includes a second conductive film made of the same material as the first conductive film, and a second silicon film.

摘要翻译： 一种半导体器件，包括设置在半导体区域的第一有源区上的第一导电类型的第一晶体管和设置在半导体区域的第二有源区上的第二导电类型的第二晶体管。 第一晶体管包括第一栅极绝缘膜和第一栅电极，第一栅极绝缘膜包含高k材料和第一金属，并且第一栅电极包括下导电膜，第一导电膜和第一硅 电影。 第二晶体管包括第二栅极绝缘膜和第二栅电极，第二栅极绝缘膜包含高k材料和第二金属，第二栅极包括由与第一导电性材料相同的材料制成的第二导电膜 膜和第二硅膜。

公开(公告)号：US06884674B2

公开(公告)日：2005-04-26

申请号：US10365502

申请日：2003-02-13

申请人： Akihiko Tsuzumitani ,  Hisashi Ogawa ,  Yasutoshi Okuno ,  Yoshihiro Mori

发明人： Akihiko Tsuzumitani ,  Hisashi Ogawa ,  Yasutoshi Okuno ,  Yoshihiro Mori

IPC分类号： H01L21/02 ,  H01L21/316 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/108

CPC分类号： H01L21/02197 ,  H01L21/02271 ,  H01L21/31691 ,  H01L27/10855 ,  H01L27/11507 ,  H01L28/55

摘要： A semiconductor device has a capacitance insulating film having a perovskite structure represented by the general formula ABO3 (where each of A and B is a metal element) and first and second electrodes opposed to each other with the capacitance insulating film interposed therebetween. The capacitance insulating film is formed such that the composition of the metal element A or B is higher in the region thereof adjacent the first electrode than in the other region thereof.

摘要翻译： 半导体器件具有电容绝缘膜，其具有由通式ABO 3（其中A和B各自为金属元素）表示的钙钛矿结构，并且第一和第二电极彼此相对地具有电容 绝缘膜插入其间。 电容绝缘膜形成为使得金属元素A或B的组成在与第一电极相邻的区域比其他区域高。

公开(公告)号：US06762445B2

公开(公告)日：2004-07-13

申请号：US10196270

申请日：2002-07-17

申请人： Hisashi Ogawa ,  Yoshihiro Mori ,  Akihiko Tsuzumitani

发明人： Hisashi Ogawa ,  Yoshihiro Mori ,  Akihiko Tsuzumitani

IPC分类号： H01L27108

CPC分类号： H01L27/10852 ,  H01L27/10894 ,  H01L28/55

摘要： In a DRAM memory cell that is a semiconductor memory device, a bit line connected to a bit line plug and local interconnect are provided on a first interlayer insulating film. A contact is not provided on a Pt film constituting an upper electrode, and a dummy lower electrode is in direct contact with a dummy barrier metal. That is, the upper electrode is connected to upper layer interconnect (Cu interconnect) by the dummy lower electrode, a dummy cell plug and the local interconnect. Since the Pt film is not exposed to a reducing atmosphere, deterioration of characteristics of a capacitive insulating film can be prevented.

摘要翻译： 在作为半导体存储器件的DRAM存储单元中，连接到位线插头和局部互连的位线设置在第一层间绝缘膜上。 在构成上电极的Pt膜上没有设置接触，并且虚拟下电极与虚拟阻挡金属直接接触。 也就是说，上电极通过虚拟下电极，虚拟电池插头和局部互连连接到上层互连（Cu互连）。 由于Pt膜不暴露于还原性气氛中，因此可以防止电容绝缘膜的特性劣化。