公开(公告)号：US20070290267A1

公开(公告)日：2007-12-20

申请号：US11763625

申请日：2007-06-15

申请人： Koh Yoshikawa ,  Setsuko Wakimoto ,  Hitoshi Kuribayashi

发明人： Koh Yoshikawa ,  Setsuko Wakimoto ,  Hitoshi Kuribayashi

IPC分类号： H01L29/76

CPC分类号： H01L29/7813 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/861

摘要： A semiconductor device is disclosed which improves the breakdown voltage of a planar-type junction edge terminating structure. The device includes an n-type semiconductor substrate layer common to an active section and an edge terminating section. An n-type drift region is formed selectively on the n-type semiconductor substrate layer in the active section and a p-type partition region is formed selectively on the n-type semiconductor substrate layer in the active section. A p-type base/body region is formed on the n-type drift region and the partition region. A source electrode is connected electrically to the p-type base/body region. A p-type partition region is formed in the edge terminating section between the p-type base/body region and the scribe plane of the semiconductor device such that the p-type partition region in the edge terminating section surrounds the p-type base/body region. A drain electrode is connected electrically to the n-type semiconductor substrate layer.

摘要翻译： 公开了一种提高平面型连接边缘端接结构的击穿电压的半导体器件。 该器件包括有源部分和边缘终止部分共同的n型半导体衬底层。 选择性地在有源部分的n型半导体衬底层上形成n型漂移区，并且在有源部分的n型半导体衬底层上选择性地形成p型分隔区。 在n型漂移区域和分隔区域上形成p型基体/体区。 源电极电连接到p型基体/体区。 在p型基体/半导体器件的划线面之间的边缘终端部形成p型分隔区域，使边缘终端部的p型分隔区域包围p型基极/ 身体区域。 漏电极与n型半导体衬底层电连接。

公开(公告)号：US07410873B2

公开(公告)日：2008-08-12

申请号：US10400171

申请日：2003-03-26

申请人： Hitoshi Kuribayashi

发明人： Hitoshi Kuribayashi

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L21/28158 ,  H01L21/28167 ,  H01L21/3247 ,  H01L29/4232 ,  H01L29/4238

摘要： A method of forming a semiconductor device uses an anneal technique to planarize and round corners of a trench formed in a substrate. The substrate is annealed under a normal pressure in an inert atmosphere, such as an atmosphere containing one of argon, helium, and neon, or an atmosphere of a gas mixture of hydrogen of 4% or less and one of argon, helium, and neon at a temperature of between 900° C. and 1050° C. for a time of between 30 seconds and 30 minutes to round the trench corners and planarize the trench side walls. Alternatively, after removing a mask for forming the trench, the substrate can be annealed in the inert atmosphere. This provides easy and inexpensive way of planarizing the trench side walls, as well as rounding of the trench corners. Moreover, by removing the mask for forming the trench before annealing enables the semiconductor device to have a highly reliable gate insulator film with good reproducibility.

摘要翻译： 形成半导体器件的方法使用退火技术来平坦化和形成在衬底中形成的沟槽的角落。 在惰性气氛中，例如氩气，氦气和氖气中的一种的气氛，或4％以下的氢气混合气体的气氛与氩气，氦气和氖气中的一种进行退火， 在900℃至1050℃之间的温度下，在30秒至30分钟之间的时间内围绕沟槽角部并平坦化沟槽侧壁。 或者，在去除用于形成沟槽的掩模之后，可以在惰性气氛中退火衬底。 这提供了简单和便宜的平面化沟槽侧壁以及沟槽角的四舍五入的方法。 此外，通过在退火之前去除用于形成沟槽的掩模，能够使半导体器件具有高可靠性的重复性良好的栅极绝缘膜。

公开(公告)号：US20060154438A1

公开(公告)日：2006-07-13

申请号：US11233377

申请日：2005-09-23

申请人： Daisuke Kishimoto ,  Hitoshi Kuribayashi ,  Yuji Sano ,  Akihiko Ohi ,  Yoshihiko Nagayasu

发明人： Daisuke Kishimoto ,  Hitoshi Kuribayashi ,  Yuji Sano ,  Akihiko Ohi ,  Yoshihiko Nagayasu

IPC分类号： H01L21/76 ,  H01L21/302

CPC分类号： H01L29/7813 ,  H01L21/02057 ,  H01L21/3065 ,  H01L21/3247 ,  H01L21/76248 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/513 ,  H01L29/66734

摘要： In the method for manufacturing a semiconductor device according to the invention including the step of forming trenches having the depth thereof in perpendicular to the major surface of a semiconductor substrate, the step of forming trenches includes the steps of performing trench etching using an insulator film, formed on the major surface of the semiconductor substrate and shaped with a predetermined pattern, for a mask to form the trenches; etching the inside of the trenches using a halogen containing gas to smoothen the inside of the trenches; and thermally treating in a non-oxidizing and non-nitriding atmosphere. The manufacturing method according to the invention facilitates well removing the etching residues remaining in the trenches and rounding the trench corners properly when the trenches are 2 μm or narrower in width and even when the trenches are 1 μm or narrower in width.

摘要翻译： 在根据本发明的半导体器件的制造方法中，包括形成其深度与半导体衬底的主表面垂直的沟槽的步骤，形成沟槽的步骤包括以下步骤：使用绝缘膜进行沟槽蚀刻， 形成在半导体衬底的主表面上并以预定图案成形，用于掩模以形成沟槽; 使用含卤素气体蚀刻沟槽的内部以平滑沟槽的内部; 并在非氧化和非氮化气氛中进行热处理。 根据本发明的制造方法有助于很好地去除残留在沟槽中的蚀刻残留物，并且当沟槽为2μm或宽度较窄时，甚至当沟槽为1μm或宽度较窄时，恰当地对沟槽角进行四舍五入。

公开(公告)号：US08080846B2

公开(公告)日：2011-12-20

申请号：US11763625

申请日：2007-06-15

申请人： Koh Yoshikawa ,  Setsuko Wakimoto ,  Hitoshi Kuribayashi

发明人： Koh Yoshikawa ,  Setsuko Wakimoto ,  Hitoshi Kuribayashi

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： H01L29/7813 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/861

摘要： A semiconductor device is disclosed which improves the breakdown voltage of a planar-type junction edge terminating structure. The device includes an n-type semiconductor substrate layer common to an active section and an edge terminating section. An n-type drift region is formed selectively on the n-type semiconductor substrate layer in the active section and a p-type partition region is formed selectively on the n-type semiconductor substrate layer in the active section. A p-type base/body region is formed on the n-type drift region and the partition region. A source electrode is connected electrically to the p-type base/body region. A p-type partition region is formed in the edge terminating section between the p-type base/body region and the scribe plane of the semiconductor device such that the p-type partition region in the edge terminating section surrounds the p-type base/body region. A drain electrode is connected electrically to the n-type semiconductor substrate layer.

摘要翻译： 公开了一种提高平面型连接边缘端接结构的击穿电压的半导体器件。 该器件包括有源部分和边缘终止部分共同的n型半导体衬底层。 选择性地在有源部分的n型半导体衬底层上形成n型漂移区，并且在有源区中的n型半导体衬底层上选择性地形成p型分隔区。 在n型漂移区域和分隔区域上形成p型基体/体区。 源电极电连接到p型基体/体区。 在p型基体/半导体器件的划线面之间的边缘终端部形成p型分隔区域，使边缘终端部的p型分隔区域包围p型基极/ 身体区域。 漏电极与n型半导体衬底层电连接。

公开(公告)号：US07510975B2

公开(公告)日：2009-03-31

申请号：US11233377

申请日：2005-09-23

申请人： Daisuke Kishimoto ,  Hitoshi Kuribayashi ,  Yuji Sano ,  Akihiko Ohi ,  Yoshihiko Nagayasu

发明人： Daisuke Kishimoto ,  Hitoshi Kuribayashi ,  Yuji Sano ,  Akihiko Ohi ,  Yoshihiko Nagayasu

IPC分类号： H01L21/302

CPC分类号： H01L29/7813 ,  H01L21/02057 ,  H01L21/3065 ,  H01L21/3247 ,  H01L21/76248 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/513 ,  H01L29/66734

摘要： In the method for manufacturing a semiconductor device according to the invention including the step of forming trenches having the depth thereof in perpendicular to the major surface of a semiconductor substrate, the step of forming trenches includes the steps of performing trench etching using an insulator film, formed on the major surface of the semiconductor substrate and shaped with a predetermined pattern, for a mask to form the trenches; etching the inside of the trenches using a halogen containing gas to smoothen the inside of the trenches; and thermally treating in a non-oxidizing and non-nitriding atmosphere. The manufacturing method according to the invention facilitates well removing the etching residues remaining in the trenches and rounding the trench corners properly when the trenches are 2 μm or narrower in width and even when the trenches are 1 μm or narrower in width.

摘要翻译： 在根据本发明的半导体器件的制造方法中，包括形成其深度与半导体衬底的主表面垂直的沟槽的步骤，形成沟槽的步骤包括以下步骤：使用绝缘膜进行沟槽蚀刻， 形成在半导体衬底的主表面上并以预定图案成形，用于掩模以形成沟槽; 使用含卤素气体蚀刻沟槽的内部以平滑沟槽的内部; 并在非氧化和非氮化气氛中进行热处理。 根据本发明的制造方法有助于很好地去除残留在沟槽中的蚀刻残留物，并且当沟槽为2μm或宽度较窄时，甚至当沟槽为1μm或宽度较窄时，恰当地对沟槽角进行四舍五入。

公开(公告)号：US07368363B2

公开(公告)日：2008-05-06

申请号：US10983243

申请日：2004-11-08

申请人： Reiko Hiruta ,  Hitoshi Kuribayashi ,  Ryosuke Shimizu

发明人： Reiko Hiruta ,  Hitoshi Kuribayashi ,  Ryosuke Shimizu

IPC分类号： H01L21/76

CPC分类号： H01L21/3247 ,  H01L21/28167 ,  H01L21/324 ,  H01L29/4236

摘要： A method of manufacturing a semiconductor device includes the steps of: exposing a semiconductor surface of a substrate; annealing the substrate in a hydrogen atmosphere at a hydrogen pressure between 200 Torr and 760 Torr and a temperature between 1000° C. and 1050° C. to planarize the exposed semiconductor surface; and forming a gate insulator film on the planarized semiconductor surface.

摘要翻译： 制造半导体器件的方法包括以下步骤：使衬底的半导体表面曝光; 在氢气气氛中在200Torr和760Torr之间的氢气压力和1000℃至1050℃之间的温度下退火衬底以平坦化暴露的半导体表面; 并在平坦化的半导体表面上形成栅绝缘膜。

公开(公告)号：US20050106847A1

公开(公告)日：2005-05-19

申请号：US10983243

申请日：2004-11-08

申请人： Reiko Hiruta ,  Hitoshi Kuribayashi ,  Ryosuke Shimizu

发明人： Reiko Hiruta ,  Hitoshi Kuribayashi ,  Ryosuke Shimizu

IPC分类号： H01L21/324 ,  H01L21/28 ,  H01L21/316 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/44 ,  H01L21/4763 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L21/3247 ,  H01L21/28167 ,  H01L21/324 ,  H01L29/4236

摘要： A method of manufacturing a semiconductor device includes the steps of: exposing a semiconductor surface of a substrate; annealing the substrate in a hydrogen atmosphere at a hydrogen pressure between 200 Torr and 760 Torr and a temperature between 1000° C. and 1050° C. to planarize the exposed semiconductor surface; and forming a gate insulator film on the planarized semiconductor surface.

摘要翻译： 制造半导体器件的方法包括以下步骤：使衬底的半导体表面曝光; 在氢气气氛中在200Torr和760Torr之间的氢气压力和1000℃至1050℃之间的温度下退火衬底以平坦化暴露的半导体表面; 并在平坦化的半导体表面上形成栅绝缘膜。

公开(公告)号：US20050106794A1

公开(公告)日：2005-05-19

申请号：US10945556

申请日：2004-09-20

申请人： Hitoshi Kuribayashi ,  Reiko Hiruta ,  Ryosuke Shimizu

发明人： Hitoshi Kuribayashi ,  Reiko Hiruta ,  Ryosuke Shimizu

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L21/28167 ,  H01L29/4236 ,  H01L29/66621

摘要： A semiconductor substrate is annealed after forming a trench in a semiconductor substrate and prior to forming a gate insulator film, at an annealing temperature T between 980° C. and 1150° C. in an atmosphere of a gas mixture containing a rare gas and hydrogen, in which the content of hydrogen is 1.3×10−18 exp(0.043T) % or lower in volume, to planarize the side wall of the trench and to round the corners of the trench at the curvature of 0.003 nm−1 or smaller. Alternatively, a semiconductor substrate with a trench formed therein is annealed prior to forming a gate insulator film, at an annealing temperature T between 980° C. and 1040° C. in an atmosphere of a gas mixture containing a rare gas and hydrogen, in which the content of hydrogen is 6.11×10−14 exp(0.0337T) % or higher in volume, to planarize the side wall of the trench but so as not to round the corners of the trench such that the curvature thereof is 0.006 nm−1 or higher. The manufacturing method according to the invention for manufacturing a semiconductor device having an insulated gate structure facilitates planarizing the gate insulator film forming region with fewer manufacturing steps and rounding the trench corners with excellent controllability.

摘要翻译： 半导体衬底在半导体衬底中形成沟槽之后，在形成栅极绝缘膜之前，在含有稀有气体和氢气的气体混合物的气氛中，在980℃至1150℃之间的退火温度T下进行退火 ，其中氢的含量为1.3×10 -6（体积）％（体积）％以下，以使沟槽的侧壁平坦化，并以沟槽的角部 0.003nm -1以下。 或者，在形成栅极绝缘膜之前，在含有稀有气体和氢气的气体混合物的气氛中，在980℃至1040℃之间的退火温度T下对其中形成有沟槽的半导体衬底进行退火， 其中氢的含量为6.11×10 -6 -14％（0.0337T）％或更高的体积，以使沟槽的侧壁平坦化，但是不会围绕沟槽的角落，使得 其曲率为0.006nm±1以上。 根据本发明的用于制造具有绝缘栅极结构的半导体器件的制造方法有利于以较少的制造步骤平坦化栅绝缘膜形成区域并且以优良的可控性对沟槽角进行四舍五入。