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    Semiconductor device test patterns and related methods for precisely measuring leakage currents in semiconductor cell transistors
    1.
    发明授权
    Semiconductor device test patterns and related methods for precisely measuring leakage currents in semiconductor cell transistors 失效
    用于精确测量半导体单元晶体管中的漏电流的半导体器件测试图案和相关方法

    公开(公告)号：US07271408B2

    公开(公告)日：2007-09-18

    申请号：US10796672

    申请日：2004-03-09

    申请人： Young-pil Kim ,  Beom-jun Jin

    发明人： Young-pil Kim ,  Beom-jun Jin

    IPC分类号： H01L23/58

    CPC分类号： H01L27/10882 ,  H01L22/32 ,  H01L27/108 ,  H01L27/10814 ,  H01L27/10894 ,  H01L27/10897 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Semiconductor device test patterns are provided that include a word line on a semiconductor substrate and an active region having a first impurity doped region and a second impurity doped region in at the semiconductor substrate. A first self-aligned contact pad is electrically connected to the first impurity doped region, and a first direct contact is electrically connected to the first self-aligned contact pad. A first bit line is electrically connected to the first direct contact, and a first probing pad is electrically connected to the first bit line. The test pattern further includes a second self-aligned contact pad that is electrically connected to the second impurity doped region, and a second direct contact electrically connected to the second self-aligned contact pad. A second conductive line is electrically connected to the second direct contact, and a second probing pad is electrically connected to the second conductive line. These test patterns may be used to measure leakage current in a cell transistor of the semiconductor device.

    摘要翻译： 提供半导体器件测试图案，其包括在半导体衬底上的字线和在半导体衬底中具有第一杂质掺杂区和第二杂质掺杂区的有源区。 第一自对准接触焊盘电连接到第一杂质掺杂区域，第一直接接触电连接到第一自对准接触焊盘。 第一位线电连接到第一直接触点，并且第一探针焊盘电连接到第一位线。 测试图案还包括电连接到第二杂质掺杂区的第二自对准接触焊盘和电连接到第二自对准接触焊盘的第二直接接触。 第二导电线电连接到第二直接接触，第二探测焊盘电连接到第二导线。 这些测试图案可用于测量半导体器件的单元晶体管中的漏电流。

    Semiconductor device having transistor and method of manufacturing the same
    2.
    发明授权
    Semiconductor device having transistor and method of manufacturing the same 有权

    公开(公告)号：US07060575B2

    公开(公告)日：2006-06-13

    申请号：US10426585

    申请日：2003-04-30

    申请人： Beom-jun Jin ,  Byeong-yun Nam ,  Young-pil Kim

    发明人： Beom-jun Jin ,  Byeong-yun Nam ,  Young-pil Kim

    IPC分类号： H01L21/336

    CPC分类号： H01L21/76897 ,  H01L21/823475 ,  H01L29/6653 ,  Y10S257/90

    摘要： A method of forming self-aligned contact holes exposing source/drain regions in a semiconductor substrate using only etch mask layers is provided. In the method, sacrificial spacers are formed of a material having an excellent etching selectivity to the etch mask layers at sidewalls of gate electrodes in a cell area. Also, an interlevel dielectric layer is formed of a material having an excellent etching selectivity to the etch mask layers. The sacrificial spacers are removed when forming the self-aligned contact holes. Dielectric spacers are formed of a material having a low dielectric constant, without considering its etching selectivity to the interlevel dielectric layer. Thus, a reduction in the operational speed of a semiconductor device having transistors can be prevented.

    Semiconductor device having transistor
    5.
    发明授权
    Semiconductor device having transistor 失效
    具有晶体管的半导体器件

    公开(公告)号：US06576963B2

    公开(公告)日：2003-06-10

    申请号：US09992069

    申请日：2001-11-14

    申请人： Beom-jun Jin ,  Byeong-yun Nam ,  Young-pil Kim

    发明人： Beom-jun Jin ,  Byeong-yun Nam ,  Young-pil Kim

    IPC分类号： H01L2976

    CPC分类号： H01L21/76897 ,  H01L21/823475 ,  H01L29/6653 ,  Y10S257/90

    摘要： A method of forming self-aligned contact holes exposing source/drain regions in a semiconductor substrate using only etch mask layers is provided. In the method, sacrificial spacers are formed of a material having an excellent etching selectivity to the etch mask layers at sidewalls of gate electrodes in a cell area. Also, an interlevel dielectric layer is formed of a material having an excellent etching selectivity to the etch mask layers. The sacrificial spacers are removed when forming the self-aligned contact holes. Dielectric spacers are formed of a material having a low dielectric constant, without considering its etching selectivity to the interlevel dielectric layer. Thus, a reduction in the operational speed of a semiconductor device having transistors can be prevented.

    摘要翻译： 提供了一种使用仅使用蚀刻掩模层在半导体衬底中暴露源/漏区的自对准接触孔的方法。 在该方法中，牺牲隔离物由对单元区域中的栅电极的侧壁处的蚀刻掩模层具有优良蚀刻选择性的材料形成。 此外，层间介电层由对蚀刻掩模层具有优异蚀刻选择性的材料形成。 当形成自对准的接触孔时，去除牺牲隔离物。 电介质间隔物由具有低介电常数的材料形成，而不考虑其对层间电介质层的蚀刻选择性。 因此，可以防止具有晶体管的半导体器件的操作速度的降低。