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1.发明授权Methods for forming and integrated circuit structures containing enhanced-surface-area conductive layers 失效包含增强表面积导电层的形成方法和集成电路结构公开(公告)号：US07253102B2
公开(公告)日：2007-08-07
申请号：US10860341
申请日：2004-06-02
IPC分类号： H01L21/4763 , H01L21/44
摘要： An enhanced-surface-area conductive layer compatible with high-dielectric constant materials is created by forming a film or layer having at least two phases, at least one of which is electrically conductive. The film may be formed in any convenient manner, such as by chemical vapor deposition techniques, which may be followed by an anneal to better define and/or crystallize the at least two phases. The film may be formed over an underlying conductive layer. At least one of the at least two phases is selectively removed from the film, such as by an etch process that preferentially etches at least one of the at least two phases so as to leave at least a portion of the electrically conductive phase. Ruthenium and ruthenium oxide, both conductive, may be used for the two or more phases. Iridium and its oxide, rhodium and its oxide, and platinum and platinum-rhodium may also be used. A wet etchant comprising ceric ammonium nitrate and acetic acid may be used. In the case of this etchant and a ruthenium/ruthenium oxide film, the etchant preferentially removes the ruthenium phase, leaving a pitted or “islanded” surface of ruthenium oxide physically and electrically connected by the underlying conductive layer. The remaining pitted or islanded layer, together with the underlying conductive layer, if any, constitutes an enhanced-surface-area conductive layer. The enhanced-surface-area conductive layer may be used to form a plate of a storage capacitor in an integrated circuit, such as in a memory cell of a DRAM or the like.
摘要翻译： 与高介电常数材料兼容的增强表面积导电层是通过形成具有至少两个相的膜或层，其中至少一个导电层是导电的。 膜可以以任何方便的方式形成，例如通过化学气相沉积技术，其后可以进行退火以更好地限定和/或结晶至少两个相。 膜可以形成在下面的导电层上。 所述至少两个相中的至少一个相被选择性地从膜上移除，例如通过蚀刻工艺，其优先蚀刻至少两个相中的至少一个，以便留下导电相的至少一部分。 导电的钌和氧化钌可以用于两个或多个相。 也可以使用铱及其氧化物，铑及其氧化物，以及铂和铂 - 铑。 可以使用包含硝酸铈铵和乙酸的湿蚀刻剂。 在这种蚀刻剂和钌/氧化钌膜的情况下，蚀刻剂优先除去钌相，留下通过下面的导电层物理和电连接的氧化钌的凹陷或“孤立”的表面。 剩余的凹陷或孤岛层与下面的导电层（如果有的话）一起构成增强的表面积导电层。 增强表面积导电层可用于在诸如DRAM等的存储单元中的集成电路中形成存储电容器的板。
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2.发明授权Methods for forming and integrated circuit structures containing enhanced-surface-area conductive layers 失效包含增强表面积导电层的形成方法和集成电路结构公开(公告)号：US06764943B2
公开(公告)日：2004-07-20
申请号：US10196535
申请日：2002-07-15
IPC分类号： H01L214763
摘要： An enhanced-surface-area conductive layer compatible with high-dielectric constant materials is created by forming a film or layer having at least two phases, at least one of which is electrically conductive. The film may be formed in any convenient manner, such as by chemical vapor deposition techniques, which may be followed by an anneal to better define and/or crystallize the at least two phases. The film may be formed over an underlying conductive layer. At least one of the at least two phases is selectively removed from the film, such as by an etch process that preferentially etches at least one of the at least two phases so as to leave at least a portion of the electrically conductive phase. Ruthenium and ruthenium oxide, both conductive, may be used for the two or more phases. Iridium and its oxide, rhodium and its oxide, and platinum and platinum-rhodium may also be used. A wet etchant comprising ceric ammonium nitrate and acetic acid may be used. In the case of this etchant and a ruthenium/ruthenium oxide film, the etchant preferentially removes the ruthenium phase, leaving a pitted or “islanded” surface of ruthenium oxide physically and electrically connected by the underlying conductive layer. The remaining pitted or islanded layer, together with the underlying conductive layer, if any, constitutes an enhanced-surface-area conductive layer. The enhanced-surface-area conductive layer may be used to form a plate of a storage capacitor in an integrated circuit, such as in a memory cell of a DRAM or the like.
摘要翻译： 与高介电常数材料兼容的增强表面积导电层是通过形成具有至少两个相的膜或层，其中至少一个导电层是导电的。 膜可以以任何方便的方式形成，例如通过化学气相沉积技术，其后可以进行退火以更好地限定和/或结晶至少两个相。 膜可以形成在下面的导电层上。 所述至少两个相中的至少一个相被选择性地从膜上移除，例如通过蚀刻工艺，其优先蚀刻至少两个相中的至少一个，以便留下导电相的至少一部分。 导电的钌和氧化钌可以用于两个或多个相。 也可以使用铱及其氧化物，铑及其氧化物，以及铂和铂 - 铑。 可以使用包含硝酸铈铵和乙酸的湿蚀刻剂。 在这种蚀刻剂和钌/氧化钌膜的情况下，蚀刻剂优先除去钌相，留下通过下面的导电层物理和电连接的氧化钌的凹陷或“孤立”的表面。 剩余的凹陷或孤岛层与下面的导电层（如果有的话）一起构成增强的表面积导电层。 增强表面积导电层可用于在诸如DRAM等的存储单元中的集成电路中形成存储电容器的板。
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3.发明授权Methods for forming and integrated circuit structures containing enhanced-surface-area conductive layers 有权包含增强表面积导电层的形成方法和集成电路结构公开(公告)号：US06482736B1
公开(公告)日：2002-11-19
申请号：US09590791
申请日：2000-06-08
IPC分类号： H01L2120
摘要： An enhanced-surface-area conductive layer compatible with high-dielectric constant materials is created by forming a film or layer having at least two phases, at least one of which is electrically conductive. The film may be formed in any convenient manner, such as by chemical vapor deposition techniques, which may be followed by an anneal to better define and/or crystallize the at least two phases. The film may be formed over an underlying conductive layer. At least one of the at least two phases is selectively removed from the film, such as by an etch process that preferentially etches at least one of the at least two phases so as to leave at least a portion of the electrically conductive phase. Ruthenium and ruthenium oxide, both conductive, may be used for the two or more phases. Iridium and its oxide, rhodium and its oxide, and platinum and platinum-rhodium may also be used. A wet etchant comprising ceric ammonium nitrate and acetic acid may be used. In the case of this etchant and a ruthenium/riruthenium oxide film, the etchant preferentially removes the ruthenium phase, leaving a pitted or “islanded” surface of ruthenium oxide physically and electrically connected by the underlying conductive layer. The remaining pitted or islanded layer, together with the underlying conductive layer, if any, constitutes an enhanced-surface-area conductive layer. The enhanced-surface-area conductive layer may be used to form a plate of a storage capacitor in an integrated circuit, such as in a memory cell of a DRAM or the like.
摘要翻译： 与高介电常数材料兼容的增强表面积导电层是通过形成具有至少两个相的膜或层，其中至少一个导电层是导电的。 膜可以以任何方便的方式形成，例如通过化学气相沉积技术，其后可以进行退火以更好地限定和/或结晶至少两个相。 膜可以形成在下面的导电层上。 所述至少两个相中的至少一个相被选择性地从膜上移除，例如通过蚀刻工艺，其优先蚀刻至少两个相中的至少一个，以便留下导电相的至少一部分。 导电的钌和氧化钌可以用于两个或多个相。 也可以使用铱及其氧化物，铑及其氧化物，以及铂和铂 - 铑。 可以使用包含硝酸铈铵和乙酸的湿蚀刻剂。 在这种蚀刻剂和钌/氧化钌氧化物膜的情况下，蚀刻剂优先除去钌相，留下氧化钌的凹陷或“孤立”的表面通过下面的导电层物理和电连接。 剩余的凹陷或孤岛层与下面的导电层（如果有的话）一起构成增强的表面积导电层。 增强表面积导电层可用于在诸如DRAM等的存储单元中的集成电路中形成存储电容器的板。
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公开(公告)号：US06812112B2
公开(公告)日：2004-11-02
申请号：US09965509
申请日：2001-09-26
IPC分类号： H01L218242
摘要： An enhanced-surface-area conductive layer compatible with high-dielectric constant materials is created by forming a film or layer having at least two phases, at least one of which is electrically conductive. The film may be formed in any convenient manner, such as by chemical vapor deposition techniques, which may be followed by an anneal to better define and/or crystallize the at least two phases. The film may be formed over an underlying conductive layer. At least one of the at least two phases is selectively removed from the film, such as by an etch process that preferentially etches at least one of the at least two phases so as to leave at least a portion of the electrically conductive phase. Ruthenium and ruthenium oxide, both conductive, may be used for the two or more phases. Iridium and its oxide, rhodium and its oxide, and platinum and platinum-rhodium may also be used. A wet etchant comprising ceric ammonium nitrate and acetic acid may be used. In the case of this etchant and a ruthenium/ruthenium oxide film, the etchant preferentially removes the ruthenium phase, leaving a pitted or “islanded” surface of ruthenium oxide physically and electrically connected by the underlying conductive layer. The remaining pitted or islanded layer, together with the underlying conductive layer, if any, constitutes an enhanced-surface-area conductive layer. The enhanced-surface-area conductive layer may be used to form a plate of a storage capacitor in an integrated circuit, such as in a memory cell of a DRAM or the like.
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公开(公告)号：US06881642B2
公开(公告)日：2005-04-19
申请号：US10419191
申请日：2003-04-21
申请人： Cem Basceri , Thomas M. Graettinger
发明人： Cem Basceri , Thomas M. Graettinger
IPC分类号： H01L21/02 , H01L21/285 , H01L21/316 , H01L21/20
CPC分类号： H01L28/84 , H01L21/02178 , H01L21/02181 , H01L21/02183 , H01L21/02194 , H01L21/0228 , H01L21/28568 , H01L21/3162 , H01L28/75 , H01L28/90
摘要： A method of forming an MIM capacitor with low leakage and high capacitance is disclosed. A layer of titanium nitride (TiN) or boron-doped titanium nitride (TiBN) material is formed as a lower electrode over an optional capacitance layer of hemispherical grained polysilicon (HSG). Prior to the dielectric formation, the first layer may be optionally subjected to a nitridization or oxidation process. A dielectric layer of, for example, aluminum oxide (Al2O3) formed by atomic layer deposition (ALD) is fabricated over the first layer and after the optional nitridization or oxidation process. An upper electrode of titanium nitride (TiN) or boron-doped titanium nitride (TiBN) is formed over the dielectric layer.
摘要翻译： 公开了一种形成具有低泄漏和高电容的MIM电容器的方法。 在半球状晶粒多晶硅（HSG）的可选电容层上形成氮化钛（TiN）或硼掺杂氮化钛（TiBN）材料层作为下电极。 在电介质形成之前，第一层可以任选地进行氮化或氧化过程。 通过原子层沉积（ALD）形成的例如氧化铝（Al 2 O 3 N）的电介质层在第一层上和在任选的氮化之后制造，或 氧化过程。 在电介质层上形成氮化钛（TiN）或硼掺杂氮化钛（TiBN）的上电极。
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公开(公告)号：US07023043B2
公开(公告)日：2006-04-04
申请号：US10039215
申请日：2002-01-03
IPC分类号： H01L29/62
CPC分类号： H01L28/65 , H01L21/31637 , H01L21/31691 , H01L23/5222 , H01L27/10852 , H01L28/56 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： An improved charge storing device and methods for providing the same, the charge storing device comprising a conductor-insulator-conductor (CIC) sandwich. The CIC sandwich comprises a first conducting layer deposited on a semiconductor integrated circuit. The CIC sandwich further comprises a first insulating layer deposited over the first conducting layer in a flush manner. The first insulating layer comprises a structure having a plurality of oxygen cites and a plurality of oxygen atoms that partially fill the oxygen cites, wherein the unfilled oxygen cites define a concentration of oxygen vacancies. The CIC sandwich further comprises a second conducting layer deposited over the first insulating layer in a strongly oxidizing ambient so as to reduce the concentration of oxygen vacancies in the first insulating layer, so as to provide an oxygen-rich interface layer between the first insulating layer and the second conducting layer, and so as to trap a plurality of oxygen atoms within the second conducting layer. The oxygen-rich interface layer and second conducting layer act as oxygen vacancy sinks for absorbing migrating oxygen vacancies that originate from the first insulating layer to thereby reduce the concentration of oxygen vacancies in the first insulating layer and to thereby reduce the buildup of oxygen vacancies at the interface layer. Thus, the first insulating layer provides an increased dielectric constant and an increased resistance to current flowing therethrough so as to increase the capacitance of the CIC sandwich and so as to reduce leakage currents flowing through the CIC sandwich.
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公开(公告)号：US07414297B2
公开(公告)日：2008-08-19
申请号：US11859116
申请日：2007-09-21
IPC分类号： H01L27/108 , H01L29/943
CPC分类号： H01L28/84 , H01L27/10817 , H01L27/10852 , H01L27/10855 , H01L28/82 , H01L28/91 , Y10S438/964
摘要： The invention includes methods of forming rugged electrically conductive surfaces. In one method, a layer is formed across a substrate and subsequently at least partially dissociated to form gaps extending to the substrate. An electrically conductive surface is formed to extend across the at least partially dissociated layer and within the gaps. The electrically conductive surface has a rugged topography imparted by the at least partially dissociated layer and the gaps. The topographically rugged surface can be incorporated into capacitor constructions. The capacitor constructions can be incorporated into DRAM cells, and such DRAM cells can be incorporated into electrical systems.
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公开(公告)号：US07274061B2
公开(公告)日：2007-09-25
申请号：US10841686
申请日：2004-05-06
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L28/84 , H01L27/10817 , H01L27/10852 , H01L27/10855 , H01L28/82 , H01L28/91 , Y10S438/964
摘要： The invention includes methods of forming rugged electrically conductive surfaces. In one method, a layer is formed across a substrate and subsequently at least partially dissociated to form gaps extending to the substrate. An electrically conductive surface is formed to extend across the at least partially dissociated layer and within the gaps. The electrically conductive surface has a rugged topography imparted by the at least partially dissociated layer and the gaps. The topographically rugged surface can be incorporated into capacitor constructions. The capacitor constructions can be incorporated into DRAM cells, and such DRAM cells can be incorporated into electrical systems.
摘要翻译： 本发明包括形成坚固的导电表面的方法。 在一种方法中，跨越衬底形成层，并且随后至少部分地解离以形成延伸到衬底的间隙。 形成导电表面以跨越至少部分解离的层并且在间隙内延伸。 导电表面具有由至少部分解离的层和间隙赋予的粗糙的形貌。 地形坚固的表面可以结合到电容器结构中。 电容器结构可以并入DRAM单元中，并且这样的DRAM单元可以被并入到电气系统中。
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9.发明授权MIM capacitor with metal nitride electrode materials and method of formation 有权具有金属氮化物电极材料的MIM电容器和形成方法公开(公告)号：US06753618B2
公开(公告)日：2004-06-22
申请号：US10093470
申请日：2002-03-11
申请人： Cem Basceri , Thomas M. Graettinger
发明人： Cem Basceri , Thomas M. Graettinger
IPC分类号： H01L2912
CPC分类号： H01L28/84 , H01L21/02178 , H01L21/02181 , H01L21/02183 , H01L21/02194 , H01L21/0228 , H01L21/28568 , H01L21/3162 , H01L28/75 , H01L28/90
摘要： An MIM capacitor with low leakage and high capacitance is disclosed. A layer of titanium nitride (TiN) or boron-doped titanium nitride (TiBN) material is formed as a lower electrode over an optional capacitance layer of hemispherical grained polysilicon (HSG). Prior to the dielectric formation, the first layer may be optionally subjected to a nitridization or oxidation process. A dielectric layer of, for example, aluminum oxide (Al2O3) formed by atomic layer deposition (ALD) is fabricated over the first layer and after the optional nitridization or oxidation process. An upper electrode of titanium nitride (TiN) or boron-doped titanium nitride (TiBN) is formed over the dielectric layer.
摘要翻译： 公开了具有低泄漏和高电容的MIM电容器。 在半球状晶粒多晶硅（HSG）的可选电容层上形成氮化钛（TiN）或硼掺杂氮化钛（TiBN）材料层作为下电极。 在电介质形成之前，第一层可以任选地进行氮化或氧化过程。 通过原子层沉积（ALD）形成的例如氧化铝（Al 2 O 3）的电介质层在第一层上和在任选的氮化或氧化过程之后制造。 在电介质层上形成氮化钛（TiN）或硼掺杂氮化钛（TiBN）的上电极。
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公开(公告)号：US07033884B2
公开(公告)日：2006-04-25
申请号：US10756621
申请日：2004-01-12
申请人： Cem Basceri , Thomas M. Graettinger
发明人： Cem Basceri , Thomas M. Graettinger
IPC分类号： H01L21/8242 , H01L21/00
CPC分类号： H01L28/40 , H01G4/1209 , H01G4/228 , H01G4/33 , H01L21/31637 , H01L21/31641 , H01L21/31645 , H01L21/31691 , H01L23/5223 , H01L27/10852 , H01L27/11502 , H01L28/56 , H01L28/75 , H01L2924/0002 , H01L2924/00
摘要： The invention includes capacitor constructions comprising a layer of aluminum oxide between a high-k dielectric material and a layer comprising titanium and nitrogen. The layer comprising titanium and nitrogen can be, for example, titanium nitride and/or boron-doped titanium nitride. The capacitor constructions can be incorporated into DRAM cells, which in turn can be incorporated into electronic systems. The invention also includes methods of forming capacitor constructions.
摘要翻译： 本发明包括在高k介电材料和包含钛和氮的层之间包含一层氧化铝的电容器结构。 包含钛和氮的层可以是例如氮化钛和/或硼掺杂的氮化钛。 电容器结构可以并入到DRAM单元中，这又可以并入到电子系统中。 本发明还包括形成电容器结构的方法。
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