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公开(公告)号：US20110320846A1
公开(公告)日：2011-12-29
申请号：US12821874
申请日：2010-06-23
IPC分类号： G06F1/26
CPC分类号： G06F1/3225 , G06F1/324 , G06F1/3275 , Y02D10/126 , Y02D10/14
摘要： Methods and apparatuses for adaptive memory operational state management. A memory performance parameter is determined for at least a portion of a memory system. The memory performance parameter is compared to one or more threshold values. An operating frequency of the memory system can be modified based on results of the comparison of the memory performance parameter and the one or more threshold values.
摘要翻译： 用于自适应存储器操作状态管理的方法和装置。 为存储器系统的至少一部分确定存储器性能参数。 将存储器性能参数与一个或多个阈值进行比较。 可以基于存储器性能参数与一个或多个阈值的比较结果来修改存储器系统的工作频率。
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公开(公告)号：US08327172B2
公开(公告)日：2012-12-04
申请号：US12821874
申请日：2010-06-23
IPC分类号： G06F1/00
CPC分类号： G06F1/3225 , G06F1/324 , G06F1/3275 , Y02D10/126 , Y02D10/14
摘要： Methods and apparatuses for adaptive memory operational state management. A memory performance parameter is determined for at least a portion of a memory system. The memory performance parameter is compared to one or more threshold values. An operating frequency of the memory system can be modified based on results of the comparison of the memory performance parameter and the one or more threshold values.
摘要翻译： 用于自适应存储器操作状态管理的方法和装置。 为存储器系统的至少一部分确定存储器性能参数。 将存储器性能参数与一个或多个阈值进行比较。 可以基于存储器性能参数与一个或多个阈值的比较结果来修改存储器系统的工作频率。
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公开(公告)号：US20090248994A1
公开(公告)日：2009-10-01
申请号：US12057132
申请日：2008-03-27
IPC分类号： G06F12/00
CPC分类号： G06F9/5016 , G06F13/28 , Y02D10/14 , Y02D10/22
摘要： A method, device, and system are disclosed. In one embodiment the method includes grouping multiple memory requests into multiple of memory rank queues. Each rank queue contains the memory requests that target addresses within the corresponding memory rank. The method also schedules a minimum burst number of memory requests within one of the memory rank queues to be serviced when the burst number has been reached in the one of the plurality of memory rank queues. Finally, if a memory request exceeds an aging threshold, then that memory request will be serviced
摘要翻译： 公开了一种方法，装置和系统。 在一个实施例中，该方法包括将多个存储器请求分组成多个存储器秩队列。 每个排队队列包含针对相应内存等级内的地址的内存请求。 当在多个存储器排队列之一中已经达到突发数目时，该方法还调度在要服务的存储器秩队列之一内的一个存储器请求中的最小突发数量。 最后，如果内存请求超过老化阈值，那么该内存请求将被服务
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公开(公告)号：US08046559B2
公开(公告)日：2011-10-25
申请号：US12057132
申请日：2008-03-27
IPC分类号： G06F12/00
CPC分类号： G06F9/5016 , G06F13/28 , Y02D10/14 , Y02D10/22
摘要： A method, device, and system are disclosed. In one embodiment the method includes grouping multiple memory requests into multiple of memory rank queues. Each rank queue contains the memory requests that target addresses within the corresponding memory rank. The method also schedules a minimum burst number of memory requests within one of the memory rank queues to be serviced when the burst number has been reached in the one of the plurality of memory rank queues. Finally, if a memory request exceeds an aging threshold, then that memory request will be serviced.
摘要翻译： 公开了一种方法，装置和系统。 在一个实施例中，该方法包括将多个存储器请求分组成多个存储器秩队列。 每个排队队列包含针对相应内存等级内的地址的内存请求。 当在多个存储器排队列之一中已经达到突发数目时，该方法还调度在要服务的存储器秩队列之一内的一个存储器请求中的最小突发数量。 最后，如果内存请求超过老化阈值，那么该内存请求将被服务。
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公开(公告)号：US09696923B2
公开(公告)日：2017-07-04
申请号：US14813097
申请日：2015-07-29
申请人： Dimin Niu , Mu-Tien Chang , Hongzhong Zheng
发明人： Dimin Niu , Mu-Tien Chang , Hongzhong Zheng
CPC分类号： G06F3/0619 , G06F3/0659 , G06F3/0688 , G06F11/1048 , G06F11/1076 , G06F12/02 , G11C5/025 , G11C5/04 , G11C5/14
摘要： A memory module (735) can include a memory array (105) and a memory controller (740). The memory controller (740) can include a status register (745) that specifies whether the memory module (735) is operating at normal power or low power. A normal reliability region (305, 505) and a low reliability region (310, 510) can be defined in the memory array (105), based on the power level specified by the status register (745).
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公开(公告)号：US09569359B2
公开(公告)日：2017-02-14
申请号：US14001464
申请日：2012-02-22
申请人： Trung Diep , Hongzhong Zheng
发明人： Trung Diep , Hongzhong Zheng
CPC分类号： G06F12/1009 , G06F12/0811 , G06F12/0864 , G06F2212/283 , G06F2212/656 , G11C7/1072
摘要： A cache memory includes cache lines to store information. The stored information is associated with physical addresses that include first, second, and third distinct portions. The cache lines are indexed by the second portions of respective physical addresses associated with the stored information. The cache memory also includes one or more tables, each of which includes respective table entries that are indexed by the first portions of the respective physical addresses. The respective table entries in each of the one or more tables are to store indications of the second portions of respective physical addresses associated with the stored information.
摘要翻译： 缓存存储器包括用于存储信息的高速缓存行。 存储的信息与包括第一，第二和第三不同部分的物理地址相关联。 高速缓存线由与存储的信息相关联的相应物理地址的第二部分索引。 高速缓冲存储器还包括一个或多个表，每个表包括由相应物理地址的第一部分索引的各个表条目。 一个或多个表中的每一个中的相应表条目是存储与存储的信息相关联的相应物理地址的第二部分的指示。
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公开(公告)号：US20130111132A1
公开(公告)日：2013-05-02
申请号：US13807095
申请日：2011-07-25
申请人： Hongzhong Zheng , Trung A. Diep
发明人： Hongzhong Zheng , Trung A. Diep
IPC分类号： G06F12/10
CPC分类号： G06F12/1063 , G06F12/0802 , G06F12/1009 , G06F12/1054
摘要： Embodiments related to a cache memory that supports tagless addressing are disclosed. Some embodiments receive a request to perform a memory access, wherein the request includes a virtual address. In response, the system performs an address-translation operation, which translates the virtual address into both a physical address and a cache address. Next, the system uses the physical address to access one or more levels of physically addressed cache memory, wherein accessing a given level of physically addressed cache memory involves performing a tag-checking operation based on the physical address. If the access to the one or more levels of physically addressed cache memory fails to hit on a cache line for the memory access, the system uses the cache address to directly index a cache memory, wherein directly indexing the cache memory does not involve performing a tag-checking operation and eliminates the tag storage overhead.
摘要翻译： 公开了与支持无标记寻址的高速缓冲存储器相关的实施例。 一些实施例接收执行存储器访问的请求，其中请求包括虚拟地址。 作为响应，系统执行地址转换操作，其将虚拟地址转换为物理地址和高速缓存地址。 接下来，系统使用物理地址访问物理寻址的高速缓存存储器的一个或多个级别，其中访问物理寻址的高速缓冲存储器的给定级别涉及基于物理地址执行标签检查操作。 如果对一个或多个物理寻址的高速缓冲存储器层的访问不能击中用于存储器访问的高速缓存行，则系统使用高速缓存地址来直接索引高速缓存存储器，其中直接索引高速缓冲存储器不涉及执行 标签检查操作，并消除标签存储开销。
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公开(公告)号：US09886194B2
公开(公告)日：2018-02-06
申请号：US14957568
申请日：2015-12-02
申请人： Hongzhong Zheng , Dimin Niu
发明人： Hongzhong Zheng , Dimin Niu
CPC分类号： G06F3/0605 , G06F3/0634 , G06F3/0679 , G06F12/0246 , G11C8/06 , G11C16/08
摘要： A system and method for using a Non-Volatile Dual In-Line Memory Module (NVDIMM) (110, 115) is disclosed. The NVDIMM (110, 115) can support two or more access modes. An application can specify which access mode is desired for an address space requested by the application. A Non-Volatile Memory (NVM) governor (150) can store an address mask and the access mode for the address space (305, 310, 315) in an NVM control register (155). When the application requests read or write access to an address (605), the NVM governor (150) can compare the requested address (605) with the address masks in the NVM control register (155), determine the access mode from the access mode corresponding to the matched address mask, and use that access mode to satisfy the request for the address (605).
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9.发明申请Decoupled Memory Modules: Building High-Bandwidth Memory Systems from Low-Speed Dynamic Random Access Memory Devices 审中-公开解耦存储器模块：从低速动态随机存取存储器件构建高带宽存储器系统公开(公告)号：US20120030396A1
公开(公告)日：2012-02-02
申请号：US13145750
申请日：2010-03-01
申请人： Zhichun Zhu , Zhao Zhang , Hongzhong Zheng
发明人： Zhichun Zhu , Zhao Zhang , Hongzhong Zheng
IPC分类号： G06F13/28
CPC分类号： G06F13/1689 , G11C8/18 , Y02D10/14
摘要： Apparatus and methods related to exemplary memory system are disclosed. The exemplary memory systems use a synchronization device to increase channel bus data rates while using relatively-slower memory devices operating at device bus data rates that differ from channel bus data rates.
摘要翻译： 公开了与示例性存储器系统相关的装置和方法。 示例性存储器系统使用同步装置来增加通道总线数据速率，同时使用在与信道总线数据速率不同的设备总线数据速率下工作的相对较慢的存储器件。
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公开(公告)号：US10133676B2
公开(公告)日：2018-11-20
申请号：US13807095
申请日：2011-07-25
申请人： Hongzhong Zheng , Trung A. Diep
发明人： Hongzhong Zheng , Trung A. Diep
IPC分类号： G06F12/00 , G06F12/1045 , G06F12/0802 , G06F12/1009
摘要： Embodiments related to a cache memory that supports tagless addressing are disclosed. Some embodiments receive a request to perform a memory access, wherein the request includes a virtual address. In response, the system performs an address-translation operation, which translates the virtual address into both a physical address and a cache address. Next, the system uses the physical address to access one or more levels of physically addressed cache memory, wherein accessing a given level of physically addressed cache memory involves performing a tag-checking operation based on the physical address. If the access to the one or more levels of physically addressed cache memory fails to hit on a cache line for the memory access, the system uses the cache address to directly index a cache memory, wherein directly indexing the cache memory does not involve performing a tag-checking operation and eliminates the tag storage overhead.
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