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    Silicon Chip Having Through Via and Method for Making the Same
    1.
    发明申请
    Silicon Chip Having Through Via and Method for Making the Same 有权
    通过硅片和其制造方法

    公开(公告)号：US20100230759A1

    公开(公告)日：2010-09-16

    申请号：US12647856

    申请日：2009-12-28

    申请人： Hsueh-An Yang ,  Pei-Chun Chen ,  Chien-Hua Chen

    发明人： Hsueh-An Yang ,  Pei-Chun Chen ,  Chien-Hua Chen

    IPC分类号： H01L23/48 ,  H01L27/092 ,  H01L21/768

    CPC分类号： H01L21/76898

    摘要： The present invention relates to a silicon chip having a through via and a method for making the same. The silicon chip includes a silicon substrate, a passivation layer, at least one electrical device and at least one through via. The passivation layer is disposed on a first surface of the silicon substrate. The electrical device is disposed in the silicon substrate, and exposed to a second surface of the silicon substrate. The through via includes a barrier layer and a conductor, and penetrates the silicon substrate and the passivation layer. A first end of the through via is exposed to the surface of the passivation layer, and a second end of the through via connects the electrical device. When a redistribution layer is formed on the surface of the passivation layer, the redistribution layer will not contact the silicon substrate, thus avoiding a short circuit. Therefore, a lower resolution process can be used, which results in low manufacturing cost and simple manufacturing process.

    摘要翻译： 本发明涉及具有贯通孔的硅芯片及其制造方法。 硅芯片包括硅衬底，钝化层，至少一个电器件和至少一个通孔。 钝化层设置在硅衬底的第一表面上。 电气设备设置在硅衬底中，并暴露于硅衬底的第二表面。 通孔包括阻挡层和导体，并且穿透硅衬底和钝化层。 通孔的第一端暴露于钝化层的表面，通孔的第二端连接电气装置。 当在钝化层的表面上形成再分布层时，再分布层将不会接触硅衬底，从而避免短路。 因此，可以使用较低分辨率的工艺，这导致制造成本低和制造工艺简单。

    Silicon Chip Having Through Via and Method for Making the Same
    2.
    发明申请
    Silicon Chip Having Through Via and Method for Making the Same 审中-公开
    通过硅片和其制造方法

    公开(公告)号：US20130032889A1

    公开(公告)日：2013-02-07

    申请号：US13569882

    申请日：2012-08-08

    申请人： Hsueh-An Yang ,  Pei-Chun Chen ,  Chien-Hua Chen

    发明人： Hsueh-An Yang ,  Pei-Chun Chen ,  Chien-Hua Chen

    IPC分类号： H01L23/522 ,  H01L27/092

    CPC分类号： H01L21/76898

    摘要： The present invention relates to a silicon chip including a silicon substrate, a passivation layer, at least one electrical device and at least one through via. The passivation layer is disposed on a first surface of the silicon substrate. The electrical device is disposed in the silicon substrate, and exposed to a second surface of the silicon substrate. The through via includes a barrier layer and a conductor, and penetrates the silicon substrate and the passivation layer. A first end of the through via is exposed to the surface of the passivation layer, and a second end of the through via connects the electrical device. When a redistribution layer is formed on the surface of the passivation layer, the redistribution layer will not contact the silicon substrate, thus avoiding a short circuit.

    摘要翻译： 本发明涉及包括硅衬底，钝化层，至少一个电气器件和至少一个通孔的硅芯片。 钝化层设置在硅衬底的第一表面上。 电气设备设置在硅衬底中，并暴露于硅衬底的第二表面。 通孔包括阻挡层和导体，并且穿透硅衬底和钝化层。 通孔的第一端暴露于钝化层的表面，通孔的第二端连接电气装置。 当在钝化层的表面上形成再分布层时，再分布层将不会接触硅衬底，从而避免短路。

    Silicon chip having through via and method for making the same
    3.
    发明授权
    Silicon chip having through via and method for making the same 有权
    具有通孔的硅芯片及其制造方法

    公开(公告)号：US08263493B2

    公开(公告)日：2012-09-11

    申请号：US12647856

    申请日：2009-12-28

    申请人： Hsueh-An Yang ,  Pei-Chun Chen ,  Chien-Hua Chen

    发明人： Hsueh-An Yang ,  Pei-Chun Chen ,  Chien-Hua Chen

    IPC分类号： H01L21/4763 ,  H01L21/44

    CPC分类号： H01L21/76898

    摘要： The present invention relates to a silicon chip having a through via and a method for making the same. The silicon chip includes a silicon substrate, a passivation layer, at least one electrical device and at least one through via. The passivation layer is disposed on a first surface of the silicon substrate. The electrical device is disposed in the silicon substrate, and exposed to a second surface of the silicon substrate. The through via includes a barrier layer and a conductor, and penetrates the silicon substrate and the passivation layer. A first end of the through via is exposed to the surface of the passivation layer, and a second end of the through via connects the electrical device. When a redistribution layer is formed on the surface of the passivation layer, the redistribution layer will not contact the silicon substrate, thus avoiding a short circuit. Therefore, a lower resolution process can be used, which results in low manufacturing cost and simple manufacturing process.

    摘要翻译： 本发明涉及具有贯通孔的硅芯片及其制造方法。 硅芯片包括硅衬底，钝化层，至少一个电器件和至少一个通孔。 钝化层设置在硅衬底的第一表面上。 电气设备设置在硅衬底中，并暴露于硅衬底的第二表面。 通孔包括阻挡层和导体，并且穿透硅衬底和钝化层。 通孔的第一端暴露于钝化层的表面，通孔的第二端连接电气装置。 当在钝化层的表面上形成再分布层时，再分布层将不会接触硅衬底，从而避免短路。 因此，可以使用较低分辨率的工艺，这导致制造成本低和制造工艺简单。

    Micro electrical mechanical system
    8.
    发明授权
    Micro electrical mechanical system 有权
    微机电系统

    公开(公告)号：US08497577B2

    公开(公告)日：2013-07-30

    申请号：US11870306

    申请日：2007-10-10

    申请人： Chien-Hua Chen ,  David M. Craig ,  Charles C. Haluzak

    发明人： Chien-Hua Chen ,  David M. Craig ,  Charles C. Haluzak

    IPC分类号： H01L23/12

    CPC分类号： B81B7/007 ,  H01L2924/16235

    摘要： An apparatus includes a Micro Electrical Mechanical System (MEMS) having electrical contacts and a MEMS device in electrical communication with the electrical contacts. A lid is oriented over the MEMS device and not the electrical contacts. The lid has a base region and a top region, the base region being wider in dimension than the top region and oriented in closer proximity to the MEMS device than the top region.

    摘要翻译： 一种装置包括具有电触头的微机电系统（MEMS）和与电触头电连通的MEMS装置。 盖子定位在MEMS器件上，而不是电触头。 盖子具有基部区域和顶部区域，基底区域的尺寸比顶部区域宽，并且被定向成比顶部区域更靠近MEMS装置。

    Semiconductor package and method for making the same
    9.
    发明授权
    Semiconductor package and method for making the same 有权
    半导体封装及其制造方法

    公开(公告)号：US08368173B2

    公开(公告)日：2013-02-05

    申请号：US12795357

    申请日：2010-06-07

    申请人： Chien-Hua Chen ,  Teck-Chong Lee

    发明人： Chien-Hua Chen ,  Teck-Chong Lee

    IPC分类号： H01L27/08

    CPC分类号： H01L28/40 ,  H01L21/76898 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/642 ,  H01L23/645 ,  H01L24/48 ,  H01L25/16 ,  H01L28/10 ,  H01L28/60 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    摘要： The present invention relates to a semiconductor package and a method for making the same. The semiconductor package includes a base material, a first metal layer, a first dielectric layer, a first upper electrode and a first protective layer. The first metal layer is disposed on a first surface of the base material, and includes a first inductor and a first lower electrode. The first dielectric layer is disposed on the first lower electrode. The first upper electrode is disposed on the first dielectric layer, and the first upper electrode, the first dielectric layer and the first lower electrode form a first capacitor. The first protective layer encapsulates the first inductor and the first capacitor. Whereby, the first inductor and the first lower electrode of the first capacitor are disposed on the same layer, so that the thickness of the product is reduced.

    摘要翻译： 半导体封装及其制造方法技术领域本发明涉及半导体封装及其制造方法。 半导体封装包括基底材料，第一金属层，第一介电层，第一上电极和第一保护层。 第一金属层设置在基材的第一表面上，并且包括第一电感器和第一下电极。 第一介电层设置在第一下电极上。 第一上电极设置在第一电介质层上，第一上电极，第一电介质层和第一下电极形成第一电容器。 第一保护层封装第一电感器和第一电容器。 由此，第一电容器的第一电感器和第一下电极设置在同一层上，从而减小了产品的厚度。